A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection

Abstract

ESD designers have to consider two shrinking design windows. On one hand, the oxide breakdown voltage of a thin-oxide transistor melted down from 12V in a 0.25µm technology to 4.5V at the 90nm node. On the other hand, the continuing demand for narrowband and broadband communication systems pushes the carrier frequencies (e.g. up to 10GHz for UWB). This reduces the tolerable capacitive load of the ESD elements. To guarantee a 2kV human body model (HBM) target, the state of the art ESD protection concepts require parasitic capacitances in the order of 100 to 150fF. This capacitive load leads to an extrapolated frequency limit of about 5GHz [1].To bridge the gap from 5GHz to frequencies >10GHz, where the implementation of shunting coils makes ESD design easier [2], the parasitic ESD capacitance can be eliminated by several compensation techniques. For narrowband RF applications, cancellation or isolation can be used [3]. Broadband RF ESD protection concepts implementing a T-coil [4] or distributed protection elements have been proposed, but they suffer from large area consumption and delicate dimensioning. Alternatively bootstrapping can be applied to screen out parasitic capacitances [5]. Here, a mid node is created by arranging two ESD elements in series as exemplarily shown in Fig. 30.7.1. If an additional sense-amplifier circuit mirrors the RF signal from the RF pad to the mid node without a time shift ∆t, no displacement current will flow over the ESD element connected to the pad. Thus, the parasitic ESD capacitance is compensated. For frequencies of ~10MHz as investigated in [5], a simple source follower could uphold the requirement ∆t→0.This work introduces a low-C ESD-protection element, referred to as dual-diode silicon-controlled rectifier (DD-SCR), with a parasitic capacitance of ~50fF, bypassing the need to cascode the ESD device for bootstrapping. The functional principle of the DD-SCR is shown in the left part of Fig. 30.7.2. It is based on a transient triggered silicon controlled rectifier (TT-SCR) as described in [1]. For a positive stress at pad 1 against V DD (abbr. PAD(pos)V DD ), the ESD current flows along the dashed-dotted line over two forwardbiased PN junctions. For a PAD(pos)V SS stress, the main discharge current will flow along the dashed line. To guarantee this, the thyristor has to be turned on by an initial trigger current through the base of the first PNP transistor of the SCR. This trigger current will flow via the forward-biased D1 and the blocking capacitance C b to ground (dotted line). The negative discharges make use of the SCR from pad1 to V DD accordingly. Adding D1 to the thyristor has 2 benefits: first, the parasitic capacitance of the SCR, that is dominated by the first PN junction at the RF pad, is reduced; secondly, the required mid-node for the bootstrap concept is created without the need of cascoding the whole ESD device.On the right side of Fig. 30.7.2, a bootstrapped version of a DD-SCR protection circuit is shown (for simplification the second thyristor is not shown...

Pseudo-Failure Impacts on ESD Robustness in Integrated Circuits I/O Ports by the Parasitic Capacitance

“…Integrated circuit (IC) component reliability relies on a standards-based evaluation. Commonly, the pass threshold of Human Body Model (HBM) in ESD standards for the commercial product (gate length ≥ 0.25-µm) is always set to be the ESD failure threshold (V ESD ) greater than 2-kV [17][18][19]. But, according to our test results, if we follow this condition to do the test, we find some products fail to pass the test.…”