BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS

Celio, Christopher; Chiu, Pi-Feng; Asanović, Krste; Nikolić, Borivoje; Patterson, David A.

doi:10.1109/mm.2019.2897782

Cited by 21 publications

(7 citation statements)

References 5 publications

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“…It is followed by CVA6 (formerly named Ariane) [44], whose design has been verified on various FPGA boards and through several tapeouts. The high number of Google Scholar hits for BOOM [18] denotes its academic importance as an OoO processor. The SHAKTI C-Class processor [27] is maintained by a slightly smaller community than BOOM and CVA6 and counts two tapeouts.…”

Section: Analysis Of Risc-v Implementationsmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

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The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology. CCS CONCEPTS• Computer systems organization → System on a chip; Serial architectures.

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Section: Analysis Of Risc-v Implementationsmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

show abstract

“…A Single Error Correction Double Error Detection (SEC-DED) code protects the caches of the SiFive U-series IPs (U54, U74) and SoC (FU540), which utilize the 5-stage in-order Rocket processor core. The BROOM tapeout [2] adds resilience methods to the 7-stage out-of-order BOOMv2 processor. Several techniques tolerate hard bit errors in L1 and L2 caches, which allows an aggressive reduction of the core voltage.…”

Section: Related Workmentioning

confidence: 99%

“…The instruction fetch unit is equipped with complex predictors (e.g., GShare and TAGE). A tapeout in TSMC 28 nm achieved 1.0 GHz and a Coremark of 3.77 per MHz [2], which makes BOOM one of the best performing RISC-V implementations. The BOOM utilizes the nonblocking L1D$ version of the Rocket, hence it is afflicted with the same ECC problems as described above.…”

Section: Rocket and Boom Processor Cores Within Chipyardmentioning

confidence: 99%

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ECC Memory for Fault Tolerant RISC-V Processors

Dorflinger

Guan

Michalik

et al. 2020

Lecture Notes in Computer Science

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Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed.

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“…These structures provide good performance, but fall short in power efficiency [2,26], especially in the post-Moore era. Furthermore, these structures also could affect the clock rate and require custom design which lags the tape-out flow of high-performance processors [10].…”

mentioning

confidence: 99%

Omegaflow

Zhou

Zhang

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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This paper investigates how to better track and deliver dependency in dependency-based cores to exploit instruction-level parallelism (ILP) as much as possible. To this end, we first propose an analytical performance model for state-of-the-art dependency-based core, Forwardflow, and figure out three vital factors affecting its upper bound of performance. Then we propose Omegaflow, a dependencybased architecture adopting three new techniques, which respond to the discovered three factors. Experimental results show that Omegaflow improves IPC by 24.6% compared to the state-of-the-art design, approaching the performance of the OoO architecture with an ideal scheduler (94.4%) without increasing the clock cycle and consumes only 8.82% more energy than Forwardflow. CCS CONCEPTS• Computer systems organization → Superscalar architectures.

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BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS

Cited by 21 publications

References 5 publications

A comparative survey of open-source application-class RISC-V processor implementations

A comparative survey of open-source application-class RISC-V processor implementations

ECC Memory for Fault Tolerant RISC-V Processors

Omegaflow

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