BSIM-IMG with improved surface potential calculation recipe

Kushwaha, Pragya; Yadav, Chandan; Agarwal, Harshit; Chauhan, Yogesh Singh; Jandhyala, Srivatsava; Khandelwal, Sourabh; Duarte, Juan Pablo; Hu, Chenming

doi:10.1109/indicon.2014.7030498

Cited by 6 publications

(2 citation statements)

References 14 publications

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“…The VT SC in FD‐SOI MOSFETs increases more with the decreasing gate length and can fall abruptly from a high applied bias or a large output swing because of the very high current gain from the built‐in parasitic bipolar and the impact‐ionization current. Other recent models featured only the long‐channel threshold‐voltage in devices with no HALO and no BTS …”

Section: Introductionmentioning

confidence: 99%

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

Tarakji

2018

Physica Status Solidi (a)

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No models exist for fully depleted silicon-on-insulator (FD-SOI) metal-oxidesilicon field-effect-transistors (MOSFETs) that operate at high currents and voltages. Operation at high currents and voltages dictates the radio-frequency (rf ) output power that such devices can deliver and transmit from the particular rf-integrated circuits used in today's cellular phones. In this work, a first order dc model for FD-SOI MOSFETs that are specifically designated to operate at high biases and large rf swings is presented. These devices typically incorporate HALO and body-tied-source (BTS), which enable much higher biases to be applied to the gate and drain and allow larger rf swings. They also employ dual-gated designs that further reduce the threshold voltage and increase the current. Although the newly established model accurately replicates the general dc behavior of any FD-SOI MOSFET that incorporates HALO and BTS, it is specifically tailored to an innovative and recently patented device structure for FD-SOI MOSFET. The new structure adopts an improved and unique design for BTS and HALO that most effectively filters the impact-ionization current to BTS and improves the device performance. New design rules that enable the designs of areaefficient layouts for FD-SOI MOSFETs that incorporate the HALO and BTS are also presented. status solidi physica a Field-Effect-Transistors www.pss-a.com

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Section: Introductionmentioning

confidence: 99%

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

Tarakji

2018

Physica Status Solidi (a)

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“…The FDSOI transistor's characteristic has frequency dependence via several inherent phenomena like the self heating effect (SHE) [18], substrate effect [13], and gate resistance effect [19]. The dc compact model is not sufficient to predict correct device behavior of measured data over a wide frequency range [20]- [24]. To capture the high-frequency behavior of the FDSOI transistor, we have enhanced the BSIM-IMG model in this work for RF applications by incorporating parasitic components like gate resistance, substrate resistance, and thermal resistance networks.…”

Section: Introductionmentioning

confidence: 99%

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Kushwaha

Khandelwal

Duarte

et al. 2016

IEEE Trans. Microwave Theory Techn.

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In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted siliconon-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.Index Terms-BSIM-IMG, compact model, fully depleted silicon-on-insulator (FDSOI), MOSFET, parameter extraction, RF.

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High-Frequency and Noise Models in BSIM-IMG

Kushwaha

Chauhan

2019

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

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BSIM-IMG with improved surface potential calculation recipe

Cited by 6 publications

References 14 publications

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

High-Frequency and Noise Models in BSIM-IMG

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