BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity

Santen, Victor M. van; Thomann, Simon; Pasupuleti, Chaitanya; Genßler, Paul R.; Gangwar, Narendra; Sharma, Uma; Henkel, Jörg; Mahapatra, S.; Amrouch, Hussam

doi:10.1109/irps45951.2020.9128342

Cited by 19 publications

(4 citation statements)

References 18 publications

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“…The HCD compact model is used to simulate the ageing of SRAM array with Sense Amplifier and Write Driver (the BTI is modeled using a physics-based simulator [6]) under actual processor workloads, refer to [27] for further details.…”

Section: Spice Simulation Of Ro Circuitsmentioning

confidence: 99%

“…Once extracted, the pure HCD time kinetics is universal in the full VG-VD space [23]. The coupled BTI-HCD compact model is used for cycle-by-cycle SPICE simulations of different gate type (inverter, NAND, NOR) RO and other complex circuits under real-life operation [26], [27]. 10 -3 This paper presents a comprehensive review of past reports from our group on HCD universality [15], pure HCD compact model that is valid across full VG-VD space [16], [17], adding BTI coupling related modifications to the pure HCD model to handle modern FETs including SH effect [23], [25], and cycleby-cycle simulation of different gate based RO circuits in the presence of BTI and HCD [26].…”

Section: Introductionmentioning

confidence: 99%

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Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Sharma

Mahapatra

2020

IEEE J. Electron Devices Soc.

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A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (VD) and gate (VG) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (VT), linear (IDLIN) and saturation (IDSAT) drain current and charge pumping current (ICP), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycleby-cycle simulation of various Ring Oscillator (RO) circuits.

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Section: Spice Simulation Of Ro Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Sharma

Mahapatra

2020

IEEE J. Electron Devices Soc.

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“…To observe the aging degradation, inverter-based ROs are commonly used. This has an important drawback since, due to the features of the inverter topology (1 PMOS and 1 NMOS transistor, without any transistor in series or parallel), relying on inverter-based ROs measurements as a foundation to predict the delay of other complex digital standard cells can lead to over-or underestimating aging effects [10] [11]. Aging affects each standard cell differently, so it is essential to measure each cell type to verify or improve the existing models.…”

Section: Introductionmentioning

confidence: 99%

A Test Module for Aging Characterization of Digital Circuits

Gata-Romero,

Santana-Andreo,

Roca

et al. 2023

2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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In digital circuits, aging phenomena can lead to timing violations due to increased signal delays suffered by digital cells. An accurate and trustworthy characterization of these mechanisms in modern nanometer CMOS technologies is essential, for which accelerated aging tests are the typical experimental procedure used. This type of test makes it possible to observe aging degradation without waiting for years of circuit operation, by raising voltage and temperature conditions above their nominal values. These stress conditions have a major impact on how the cell under test will be affected by aging degradation. This paper presents a new highly versatile test module whose purpose is to generate AC and DC signals with different amplitudes and, in the case of AC signals, also with different frequencies, to stress a digital cell in a wide variety of scenarios.

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“…These phenomena lead to malfunction in circuits. From BTI to BEOL TDDB, there are numerous studies for their impact on device, circuit, and system performance and reliability [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], but they are not the topic discussed here. In this paper, our attention is focused on recent progress in physics-based modeling of EM in on-chip interconnects.…”

Section: Introductionmentioning

confidence: 99%

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity

Cited by 19 publications

References 18 publications

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

A Test Module for Aging Characterization of Digital Circuits

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

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BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity

Cited by 19 publications

References 18 publications

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

A Test Module for Aging Characterization of Digital Circuits

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

Contact Info

Product

Resources

About

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures