2022 IEEE 2nd International Conference on Power, Electronics and Computer Applications (ICPECA) 2022
DOI: 10.1109/icpeca53709.2022.9719205
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Buffer Reduction for Congestion Control during Timing Optimization

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Cited by 3 publications
(2 citation statements)
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“…Consequently, the register clustering method efficiently reduces the capacitance of leaf-level buffers and generates the leaf-level topographical structure of the clock tree [7]. By integrating the register clustering method into the traditional CTS process, the power consumption of the clock network and clock skew can be effectively reduced [8].…”
Section: Problem Definitionmentioning
confidence: 99%
“…Consequently, the register clustering method efficiently reduces the capacitance of leaf-level buffers and generates the leaf-level topographical structure of the clock tree [7]. By integrating the register clustering method into the traditional CTS process, the power consumption of the clock network and clock skew can be effectively reduced [8].…”
Section: Problem Definitionmentioning
confidence: 99%
“…In the design of digital IC back-ends, the clock tree technique is usually used to solve this inconsistency problem [ 9 , 10 ]. However, in the process of designing and manufacturing large-pixel-array CMOS image sensors, stitching technology is used to improve the consistency of the column readout circuit and reduce the manufacturing cost, so the clock tree technique cannot synchronize bilateral row driver signals.…”
Section: Introductionmentioning
confidence: 99%