Buffer Traps Effect on GaN-on-Si High-Electron-Mobility Transistor at Different Substrate Voltages

Abstract

Substrate voltage (VSUB) effects on GaN-on-Si high electron mobility transistors (HEMTs) power application performance with superlattice transition layer structure was investigated. The 2DEG conductivity and buffer stack charge redistribution can be affected by neutral/ionized donor and acceptor traps. As the donor/acceptor traps are excessively ionized or de-ionized by applying VSUB, the depletion region between the unintentionally doped (UID)/Carbon-doped (C-doped) GaN layer may exhibit a behavior similar to the p–n junction. An applied negative VSUB increases the concentration of both the ionized donor and acceptor traps, which increases the breakdown voltage (BV) by alleviating the non-uniform distribution of the vertical electric field. On the other hand, an applied positive VSUB causes the energy band bending flattener to refill the ionized traps and slightly improves the dynamic Ron degradation. Moreover, the amount of electrons injected into the buffer stack layer from the front side (2DEG channel/Ohmic contact) and the back side (AlN nucleation layer/superlattice transition layer) are asymmetric. Therefore, different VSUB can affect the conductivity of 2DEG through the field effect, buffer trapping effect, and charge redistribution, which can change the electrical performance of the device.

Analysis and simulation of bulk polarization mechanism in p-GaN HEMT with AI component gradient buffer layer

“…Due to the gate electric field concentration and buffer leakage of GaN devices, it is easy to cause device breakdown ahead of time, and the average breakdown electric field * Author to whom any correspondence should be addressed. is much lower than that of GaN materials [8]. To reduce buffer leakage, back-barrier technology [9], superlattice technology [10], and buffer doping are conventional methods [11,12].…”

Analysis of Trapping Effect on Large-Signal Characteristics of GaN HEMTs Using X-Parameters and UV Illumination

“…However, the reliability issues related to gate leakage and current collapse degrades the output power and efficiency of GaN-based devices [ 7 , 8 ]. The current collapse phenomena are associated with the presence of charge trapping states at the surface, or in the GaN buffer [ 9 , 10 ]. One of the popular methods for reducing the gate leakage current is introducing a SiN gate dielectric layer under the metal gate.…”