Buffered clock tree synthesis for 3D ICs under thermal variations

Minz, J.R.; Zhao, Xin; Lim, Sung Kyu

doi:10.1109/aspdac.2008.4484003

Cited by 50 publications

(76 citation statements)

References 8 publications

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“…Such high quality clock trees fully utilizing 3D design space can span entire dies as shown in Fig. 1 [7][8][9][10][11][12][13][14]. To safely apply highly optimized 3D clock trees distributed on multiple dies to a main production process of 3D ICs, we need to consider a new 3D process variation issue which is a special item distinguished from the conventional process variation for 2D clock trees.…”

Section: D Clock Tree and On-package Variationmentioning

confidence: 99%

“…Minz, Zhao, and Lim [7] minimize and balance temperature dependent skew by relocating merging points of an initial zero skew clock tree. They also provided detail analysis to show low power clocking property of the multi-TSV approach compared to the single-TSV approach in the work [8].…”

Section: Introductionmentioning

confidence: 99%

“…For the buffered clock tree designs, 3D clock tree synthesis (CTS) algorithms are studied in the works [7][8][9][10]. Minz, Zhao, and Lim [7] minimize and balance temperature dependent skew by relocating merging points of an initial zero skew clock tree.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Kim¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

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Section: D Clock Tree and On-package Variationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Kim¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

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“…Minz et al [10] presented a 3D clock routing algorithm under the wirelength minimization goal. Their 3D tree has a unique property, where only one of the dies in the stack contains a fully connected 2D clock tree while the other dies contain many small, isolated subtrees.…”

Section: Introductionmentioning

confidence: 99%

Pre-bond testable low-power clock tree design for 3D stacked ICs

Zhao

Lewis

Lee

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree for the pre-bond testing. In addition, the entire 3D stack needs a complete 3D clock tree for post-bond testing and normal operations. In the case of two-die stack, a straightforward solution is to have two complete 2D clock trees connected with a single Through-Silicon-Via (TSV). We show that this solution suffers from long wirelength and high clock power consumption. Instead, our algorithm minimizes the overall wirelength and clock power consumption while providing the pre-bond testability and post-bond operability under given skew and slew constraints. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approach significantly reduces the clock power by up to 15.9% for two-die and 29.7% for four-die stack. In addition, the wirelength reduction is up to 24.4% and 42.0%.

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“…Recent papers consider thermal effects on buffered 3-D clock trees [1] and H-tree topologies [2], [3]. No experimental characterization of 3-D clock distribution networks, however, has been presented.…”

Section: Introductionmentioning

confidence: 99%