Bug identification of a real chip design by symbolic model checking

Chen, B.; Yamazaki, Masami; Fujita, M.

doi:10.1109/edtc.1994.326886

Cited by 31 publications

(10 citation statements)

References 3 publications

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“…We used SMV [1] as our model checker because it has many good features to support real designs and there are many success stories from the industry [2][3] [4][5] [6] [7]. SMV supports various features to reduce the problem size, i.e., the scalarset data type for symmetric reduction, the ordset data type for induction, the subclass structure for case-splitting, the layer structure for the compositional assume-guarantee verification, and the property based reduction capability.…”

Section: Model Checker and Languagementioning

confidence: 99%

Model checking of S3C2400X industrial embedded SOC product

Choi

Yun

Lee

et al. 2001

Proceedings of the 38th Conference on Design Automation - DAC '01

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This paper describes our experience and methodology used in the model checking of S3C2400X industrial embedded SOC product. We employed model checking to verify the RTL implementation. We describe how to model the multiple clocks, gated clocks, unsynchronized clocks, and synchronization logics in model checking. Detailed case studies of real designs show the application of the proposed modeling techniques, environment modeling, and the properties we checked. The verification results validate the proposed techniques by finding real bugs.

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Section: Model Checker and Languagementioning

confidence: 99%

Model checking of S3C2400X industrial embedded SOC product

Choi

Yun

Lee

et al. 2001

Proceedings of the 38th Conference on Design Automation - DAC '01

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“…While offering the benefits of simplicity and scalability, simulation offers no guarantees of correctness; for large designs, the fraction of the design space which can be covered in this methodology is vanishingly small. Indeed, there are many examples of designs that passed extensive simulation, but were still found to contain bugs [5]. This has led to the proposal of "formal methods" for design verification.…”

Section: Introductionmentioning

confidence: 99%

Hybrid verification using saturated simulation

Aziz

Kukula

Shiple

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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We develop a verification paradigm called saturated simulation, that is applicable to designs which can be decomposed into a set of interacting controllers. The core procedure is a symbolic algorithm that explores the space of controller interactions; heuristics for making this traversal efficient are described. Experiments demonstrate that our procedure explores substantially more of the controller interactions, and is more efficient than conventional symbolic reachability analysis.

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“…These, however, were done manually or at most semi-automatically which might not be very practical for a large design. Moreover, the work in [6] and [10] do not provide a formal proof for the soundness of the reduction or composition used during the verification. In this paper, we present our results of formally verifying the TMRS Telecom megacell using FormalCheck where not only the model abstraction and reduction are done automatically, but also the normal operating environment of the design is defined inside the tool.…”

Section: Introductionmentioning

confidence: 99%

“…al. [6] on the verification of an ATM (Asynchronous Transfer Mode) circuit at Fujitsu using the SMV model checker. Lu et.…”

Section: Introductionmentioning

confidence: 99%

Practical approaches to the verification of a telecom megacell using FormalCheck

Barakatain

Tahar

Lamarche³

et al. 2001

Proceedings of the 11th Great Lakes Symposium on VLSI

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In this paper we present practical approaches to formally verify the RTL implementation of a Telecom megacell using model checking techniques based on the FormalCheck tool. We adopted a hierarchical verification method, which relies on the built-in hierarchy of the design as the mechanism to conquer its verification complexity. We then applied a number of tool guided abstraction and reduction techniques within FormalCheck to avoid state space explosion. The case study we considered is the Transmit Master/ Receive Slave (TMRS) Telecom megacell from PMC-Sierra, Inc., implementing a SCI-PHY (Saturn Compatible Interface for ATM-PHY devices) protocol. Using our approaches, we succeeded the model checking of the TMRS design and were able to uncover a number of flaws in the RTL design as well as in the documentation specification.

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Bug identification of a real chip design by symbolic model checking

Cited by 31 publications

References 3 publications

Model checking of S3C2400X industrial embedded SOC product

Model checking of S3C2400X industrial embedded SOC product

Hybrid verification using saturated simulation

Practical approaches to the verification of a telecom megacell using FormalCheck

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