The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1][2][3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4,5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.The proposed pseudo-multiple sampling technique is described in Fig. 22.2.1. The basic concept of pseudo-multiple sampling is dividing an A/D conversion into several lower resolution A/D conversions. The quantization step of each lower resolution A/D conversion is M times larger than that of normal A/D conversion where M is the number of pseudo-multiple sampling. Each quantization level of lower resolution A/D conversion has 1 LSB offset of normal A/D conversion to ensure the final result has the same resolution of normal A/D conversion. The final result can be calculated by adding all lower resolution A/D conversion results.The output noise of each lower resolution A/D conversion is approximately 1/M times lower than that of normal A/D conversion, when the input noise standard deviation is higher than the quantization step of lower resolution A/D conversion. Therefore, the output noise of the pseudo-multiple sampling A/D conversion is 1/√M times lower than that of normal A/D conversion, if the noise is completely uncorrelated. It is same as the conventional multiple sampling. However, the noise reduction effect of the pseudo-multiple sampling is limited, although the number of sampling is increased. It is because if the quantization step of lower resolution A/D conversion is higher than the input noise standard deviation, some of lower resolution A/D conversion cannot express the input noise properly. Figure 22.2.2 is the noise reduction simulation result of the conventional multiple sampling and the pseudo-multiple sampling using an ideal A/D converter with input noise applied. The noise is assumed white Gaussian having standard deviation of σ in in normal A/D conversion LSB unit. The simulation result shows the noise reduction performance of the pseudo-multiple sampling is almost same as that of the conventional multiple sampling up to M=σ in , and the output noise is saturated to 0.75×√σ in when M is higher than 4σ in .The pseudo-multiple sampling can be implemented using a conventional single slope ADC structure by altering o...

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This paper describes our experience and methodology used in the model checking of S3C2400X industrial embedded SOC product. We employed model checking to verify the RTL implementation. We describe how to model the multiple clocks, gated clocks, unsynchronized clocks, and synchronization logics in model checking. Detailed case studies of real designs show the application of the proposed modeling techniques, environment modeling, and the properties we checked. The verification results validate the proposed techniques by finding real bugs.

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