Building blocks for future dual-channel GaN gate drivers: Arbitrary waveform driver, bootstrap voltage supply, and level shifter

Abstract

Capitalising on the high-speed switching capability of 650 V GaN FETs in power-electronic bridgelegs is challenging. Whilst active gate driving has previously been shown to help overcome adverse switching behaviour, the best results are likely to be achieved through a combination of uncompromised circuit layout and active gate driving. A fully integrated dual-channel driver would minimise external circuitry and allow power devices to be placed as close together as possible. This would facilitate simultaneous minimization of parasitic inductances in the gate-drive and power-circuit loops. Other benefits would include ease of use, lower BOM cost, and providing a step towards full integration of driver and power stage. This paper presents three circuit blocks vital to the implementation of a fully integrated dual-channel gate driver-A 100 ps resolution, digitally-controlled active gate driver IC, a sub-ns propagation delay level shifter with 200 V/ns slew-rate immunity, and a regulated bootstrap supply that maintains its output voltage regardless of any switch-node undershoot during switching events. Measurement results show the efficacy of the high-resolution active gate driver in a GaN bridge leg, and the sub-ns propagation delay of the level shifter, both fabricated in a 50 V CMOS process. Simulation results demonstrate the slew-immunity of the level shifter, and operation of the bootstrap supply. It is also inferred how to increase the voltage rating of the level-shifter and bootstrap without adversely affecting performance.

Current Trends in the Development of Normally-OFF GaN-on-Si Power Transistors and Power Modules: A Review

“…Such waveform shaping techniques, on the gate or switching nodes of the GaN-based circuit, have also been implemented in the E-mode GaN driver ICs. [81][82][83][84] The primary goal of current gate driver designs is to improve reliability and power conversion efficiency and to reduce EMI noise of the GaN power devices in practical applications. As a result, dynamic adjustments of the gate driving strength for safe and efficient switching with fast dead-time corrections are active research areas.…”

Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN

“…Switching times of wide bandgap power transistors are extremely high (hundreds of V/ns for 600V GaN or 1.2kV SiC MOSFET) [1]. Therefore, practical useful guidelines are provided to the designer to determine the best trade-off in terms of integrated high voltage capacitive dv/dt sensor (CS), current mirror gain and PMOS/NMOS transistors sizes in order to design an integrated dv/dt control system [2]- [4].…”