Building-in reliability: soft errors-a case study

Hasnain, Zille; Ditali, A.

doi:10.1109/relphy.1992.187657

Cited by 11 publications

(5 citation statements)

References 3 publications

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“…However, after considerable early activity, the terrestrial soft error problem was effectively alleviated by using low-activity materials and on-chip shielding coatings [5], [6]. Occasionally, changes in suppliers or procedures have caused semiconductor manufacturers temporary but considerable headaches due to raised radioactive contaminant levels in materials such as nitric and phosphoric acid [5], [166]. The march toward higher integration densities has made soft-error concerns a continual design consideration for advanced DRAM and SRAM development in the last decade.…”

Section: Terrestrial and High-altitude Seesmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

903

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: Terrestrial and High-altitude Seesmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

903

427

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“…Due to their proximity to active elements, the flip-chip solder interconnects should have minimal levels of alpha-particle radiation to limit soft errors in complementary metal-oxide semiconductor (CMOS) technology that become more critical as cell size on the die is reduced. 16,17 The elemental constituents of lead-free solders (tin, copper, silver, bismuth, indium, and antimony) do not radioactively decompose, so alphaparticle radiation is minimal.…”

Section: Introductionmentioning

confidence: 99%

Pb-free solders for flip-chip interconnects

Frear

Jang

Lin

et al. 2001

JOM

300

196

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Editor's Note: A hypertext-enhanced version of this article can be found at www.tms.org/pubs/journals/JOM/0106/ Frear-0106.html A variety of lead-free solder alloys were studied for use as flip-chip interconnects including , and eutectic Sn-37Pb as a baseline. The reaction behavior and reliability of these solders were determined in a flip-chip configuration using a variety of under-bump metallurgies (TiW/Cu, electrolytic nickel, and electroless Ni-P/Au). The solder microstructure and intermetallic reaction products and kinetics were determined. The Sn-0.7Cu solder has a large grain structure and the Sn-3.5Ag and Sn-3.8Ag-0.7Cu have a fine lamellar two-phase structure of tin and Ag 3 Sn. The intermetallic compounds were similar for all the lead-free alloys. On Ni, Ni 3 Sn 4 formed and on copper, Cu 6 Sn 5 Cu 3 Sn formed. During reflow, the intermetallic growth rate was faster for the lead-free alloys, compared to eutectic tin-lead. In solidstate aging, however, the interfacial intermetallic compounds grew faster with the tinlead solder than for the lead-free alloys. The reliability tests performed included shear strength and thermomechanical fatigue. The lower strength Sn-0.7Cu alloy also had the best thermomechanical fatigue behavior. Failures occurred near the solder/intermetallic interface for all the alloys except Sn-0.7Cu, which deformed by grain sliding and failed in the center of the joint. Based on this study, the optimal solder alloy for flip-chip applications is identified as eutectic Sn-0.7Cu.

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“…By definition, a hardware device can recover its full capability following a transient failure, but such failures are no less catastrophic for the correct execution of a program because a corrupted intermediate value, if not handled, can corrupt all subsequent computations. Over the years, measures to protect against soft errors in memory devices have evolved to include physical techniques in cell/gate design [1] and packaging materials [9], as well as error correction codes (ECC). Today, these techniques are commonplace even in commodity PC memories, but, except in extremely critical applications, protection against transient failures has received little commercial attention outside of the memory subsystem.…”

Section: Transient Hardware Faultsmentioning

confidence: 99%