Effect of wafer bow on electrostatic chucking and back side gas cooling Estimation of wafer warpage profile during thermal processing in microlithography Rev. Sci. Instrum. 76, 075111 (2005); 10.1063/1.1979468 Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

Ultrathin dielectric materials that provide high capacitance values are needed for 64-and 256-Mb stacked DRAM's. This paper shows that capacitance values as high as 12.3 fF/pmZ can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. In addition, these films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thickness, however, cannot be scaled much below 6 nm to avoid the oxidationpunchthrough mechanisms that appear when too-thin films are unable to withstand the reoxidation step.

No abstract

No abstract

The reliability and electrical properties of planar and 3D interpoly oxide/nitride films stacked on multi-megabit dynamic random access memory (DRAM) array topography are reported to determine their thinning and capacitance limits. A compromise between reliability, leakage current, and storage capacity is proposed for oxidized low-pressure chemical vapor deposited nitride layers with different nitride thicknesses, oxidation conditions, and top/bottom polysilicon doping levels. Capacitance, leakage current, and time-dependent dielectric breakdown measurements show that thinner nitride layers with longer oxidation times provide the maximum lifetime and capacitance. However, the nitride thinning is limited when leakage current by Poole-Frenkel or Fowler-Nordheim emission occurs. For 5 V operated high-density DRAMs, nitride layers as thin as 7 nm, giving a capacitance of 6 fF/~m 2 present the optimum conditions. For 3.3 V operations, films as thin as 4-5 nm, giving a capacitance of 9 fF/~m 2, can be expected.