Ultrathin oxide-nitride dielectrics for rugged stacked DRAM capacitors

Abstract

Ultrathin dielectric materials that provide high capacitance values are needed for 64-and 256-Mb stacked DRAM's. This paper shows that capacitance values as high as 12.3 fF/pmZ can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. In addition, these films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thickness, however, cannot be scaled much below 6 nm to avoid the oxidationpunchthrough mechanisms that appear when too-thin films are unable to withstand the reoxidation step.

High capacitance density highly reliable textured deep trench SiN capacitors toward 3D integration

“…The texture was formed by rugged poly-Si formation, 35,36) which had been used for the DRAM capacitors to expand the surface area. [37][38][39][40][41][42][43][44] SiN dielectric film was formed by low-pressure CVD (LPCVD). The buried electrode to fill in the trench is n + doped poly-Si formed also by LPCVD.…”

Sixteen-megabit dynamic random access memory trench depth characterization using two-dimensional diffraction analysis

“…3 Alternative new methods for increasing cell charge capacity without increasing cell depth include reducing the dielectric thickness or increasing the dielectric constant. 4 However, reducing the nitride thickness below 6 nm causes sudden drops in capacitance, 5,6 while adopting materials with higher dielectric constants, e. g., tantalum pentoxide ͑Ta 2 O 5 ͒, results in higher leakage current levels. 5 Even though these methods are promising future techniques, they are currently far from mature, and vertical topography is still the method of choice for present and future DRAM technology.…”

“…4 However, reducing the nitride thickness below 6 nm causes sudden drops in capacitance, 5,6 while adopting materials with higher dielectric constants, e. g., tantalum pentoxide ͑Ta 2 O 5 ͒, results in higher leakage current levels. 5 Even though these methods are promising future techniques, they are currently far from mature, and vertical topography is still the method of choice for present and future DRAM technology. 1 As trenches of high megabit ͑MB͒ DRAMs get deeper and thinner, the aspect ratio of trenches, defined as the trench's height divided by its width, becomes large ͑у7 for 16-MB DRAM͒.…”

A high-C capacitor (20.4 fF/ mu m/sup 2/) with ultrathin CVD-Ta/sub 2/O/sub 5/ films deposited on rugged poly-Si for high density DRAMs

“…To build 64 and 256 Mb stacked memory chips, considerably higher capacitance values are needed to keep the cell structures simple and manufacturable. For this purpose, high dielectric constant Ta2O5 films (1,(3)(4)(5)(6) or ON films on rugged poly-Si bottom electrodes (7-11) have been proposed recently and have givcen capacitance values as high as 12 fF/pn2 (1,5,10,11). Integrity reactor at 400 or 450°C, using Ta(OC2Hs)s and 02 (6).…”