Effects of wafer bow and warpage on the integrity of thin gate oxides

Thakur, R. P. S.; Chhabra, Nitin; Ditali, A.

doi:10.1063/1.111231

Cited by 23 publications

(8 citation statements)

References 6 publications

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“…It is well reported that the hot-carrier reliability in MOSFET is signicantly improved by smoothing the surface, homogenous interface state, and a low defects in the near drain junctions; however the MOSFETs did not consider the substrate thermal stress due to is extremely low stress level. [28][29][30] The thermal substrate stress can affect several factors, such as grain boundary density, microcracks, interface bonding state, and surface smoothness.…”

Section: Resultsmentioning

confidence: 99%

Tempered glass substrate effect on the growth of polycrystalline-silicon and its applications for reliable thin-film transistors

et al. 2015

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Section: Resultsmentioning

confidence: 99%

Tempered glass substrate effect on the growth of polycrystalline-silicon and its applications for reliable thin-film transistors

et al. 2015

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“…There are many factors contributing to wafer warpage, such as coefficient of thermal expansion (CTE) mismatch, thickness of films and pattern density [4][5]. Wafer warpage induced stress is one of the root causes leading to process and device failure such as delamination, cracking, and decrease in device performance [6][7]. Therefore, it is crucial to reduce wafer warpage through process optimization for TSV wafer.…”

Section: Introductionmentioning

confidence: 99%

Wafer level warpage modeling methodology and characterization of TSV wafers

Zhang

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.

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“…This plastic deformation gives rise to pattern misalignment, device failure, generation of defects in dielectric films, etc. 1 Much effort has been made to study this problem of thermal stress in RTP. Vandenabeele et al showed direct experimental evidence that pattern induced temperature nonuniformity could cause plastic deformation.…”

Section: Introductionmentioning

confidence: 99%

Thermal stress at wafer contact points in rapid thermal processing investigated by repeated spike treatment before oxidation

Hong

Chang

Lee

et al. 2003

Journal of Applied Physics

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Repeated spike treatment ͑RST͒, which was characterized by setting the temperature to ramp up and down repeatedly, was employed to study the stress effect on wafers by annealing the silicon wafers in ambient N 2 , followed by oxidation in O 2 . These RSTϩO samples had three apparent local thick oxide regions that adjoined the contacts of the three-pin quartz holder, as opposed to the typicalϩO samples annealed with a conventional temperature profile before the same oxidation process. It was observed that defects could be created on the silicon surface due to the high thermal stress at contacts during RST, and that the oxidation rate of these damaged zones was greatly increased. I-V data show that for a similar oxide thickness, the leakage currents in RSTϩO samples are higher and more scattered than those in typicalϩO samples. C-V measurements illustrate that RSTϩO samples have higher interface state densities than typicalϩO samples. These enhanced degradation phenomena could be caused by the RST, which resulted in a rough Si/SiO 2 interface and nonuniform oxide thickness.

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Effects of wafer bow and warpage on the integrity of thin gate oxides

Abstract: Effect of wafer bow on electrostatic chucking and back side gas cooling Estimation of wafer warpage profile during thermal processing in microlithography Rev. Sci. Instrum. 76, 075111 (2005); 10.1063/1.1979468 Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

Cited by 23 publications

References 6 publications

Tempered glass substrate effect on the growth of polycrystalline-silicon and its applications for reliable thin-film transistors

Tempered glass substrate effect on the growth of polycrystalline-silicon and its applications for reliable thin-film transistors

Wafer level warpage modeling methodology and characterization of TSV wafers

Thermal stress at wafer contact points in rapid thermal processing investigated by repeated spike treatment before oxidation

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