Built in self test architecture for testing SRAM using transient current testing

Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST. Achieving considerable reduction in test time. Previous works or symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, giver the large number of memories available in current chips, increase the hardware overhead of the BIST circuitry.In this work we propose a Symmetric transparent BIST scheme that can be utilized to test Rams. For 5 different word widths hence, more than one RAMs can be tested in a roving manner. The hardware overhead of the proposed scheme is considerably smaller compared to the utilization of previously proposed symmetric transparent schemes.

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Built in self test architecture for testing SRAM using transient current testing

Cited by 3 publications

References 10 publications

Built in self-test scheme for SRAM memories

Built in self-test scheme for SRAM memories

An efficient fault detection technique in SRAM using wavelet transform

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