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In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5.Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.

In this paper a multiplexer based S-box architecture with 5 stage pipelining is proposed The proposed AES S-box were implemented on Xilinx device XC5VLX20T Virtex-5 FPGA. The results are compared with modular design architecture.This implementation gives 10.55 ns path delay with the slice area of 52 without pipelining and 1.74 ns path delay with the slice area of 36 by introducing 5 stage pipelining. The results show that the pipelined modified structure reduces the critical path so the through put is increased to 4.5Gbps. Keywords-Advanced Encryption Standard (AES), composite field arithmetic (CFA), multiplicative inversion.I.

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In recent years, it is necessary to protect individual privacy from unauthenticated persons. This paper presents a biometric encryption using face recognition system to identify known and unsuspected persons in watch list applications. The face recognition system is done by the Eigen face approach by PCA algorithm to simplify the authentication process, then to secure the Eigen faces generate the cryptographic key (RNG) and which key is bind that facial images. The faces are accepted as known or unknown face by after verification with present database.