Built-in self-test for signal integrity

Nourani, Mehrdad; Attarha, Amir

doi:10.1145/378239.379068

Cited by 32 publications

(21 citation statements)

References 23 publications

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“…Test patterns causing worst-case SI loss can be used [15], [16]. Pseudorandom patterns have also been investigated [15], [27]. Recently, it has been suggested to use pseudo-exhaustive testing of SI for high-speed SoC interconnects [28].…”

Section: A Test Methodologymentioning

confidence: 99%

“…The proposed test architecture has been adapted from [15] and [27]. Let us assume that the identification of an SIV event is required.…”

Section: F Test Architecturementioning

confidence: 99%

“…A violation is identified when the AND output goes to 1 logic. For diagnosis purposes, the test architecture proposed in [15] and [27] can be used. When a multisignal monitor is used, the number of required flip-flops is reduced.…”

Section: F Test Architecturementioning

confidence: 99%

See 2 more Smart Citations

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

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Abstract-Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

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Section: A Test Methodologymentioning

confidence: 99%

“…The proposed test architecture has been adapted from [15] and [27]. Let us assume that the identification of an SIV event is required.…”

Section: F Test Architecturementioning

confidence: 99%

See 1 more Smart Citation

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

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“…Bai et al [2000] introduced on-chip test generators and error detectors at the core boundaries, based on the MA fault model [Cuviello et al 1999]. Nourani and Attarha [2001] presented two ILS cell designs to detect voltage distortions and timing violations, respectively. Later, several other ILS designs [Caignet et al 2001;Tabatabaei and Ivanov 2002] were introduced, which are more accurate in measuring voltage and/or timing violations, at the cost of large area overheads.…”

Section: Related Work and Motivationmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

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“…Based on the MA fault model a semi-BIST circuitry and a defect simulation method were developed [10]. Although MA significantly simplifies the problem for interconnects modeled as RC circuits, it suffers from lack of precision needed for accurate RLC interconnect models [11]. In [12], the authors presented a BIST-based methodology for testing interconnects for noise and skew in gigahertz SoCs and discuss the adverse effects of overshoot on SoC reliability.…”

Section: Prior Workmentioning

confidence: 99%