Test pattern generation for signal integrity faults on long interconnects

Attarha, Amir; Nourani, Mehrdad

doi:10.1109/vts.2002.1011162

Cited by 30 publications

(11 citation statements)

References 27 publications

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“…Early attempts for testing SI-related problems modeled crosstalk at the circuit level [Attarha and Nourani 2002;Chen et al 1999]. Although more accurate than gate-level models, the complexity of the associated test-pattern generation procedures limits its usefulness for SOC interconnects.…”

Section: Related Work and Motivationmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

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Section: Related Work and Motivationmentioning

confidence: 99%

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Zhang

Chakrabarty

2009

ACM Trans. Des. Autom. Electron. Syst.

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“…The details are beyond the scope of this paper and can be found in [38]. Briefly, the input to an interconnect network, i t ¡ , can be expressed as:…”

Section: Deterministic Pattern Generationmentioning

confidence: 99%

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

Nourani

Attarha

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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“…Since previous works [1][2][3][4][5][6][7][8][9] did not consider the effect of interconnection topology, their accuracy is much more decreased. For the effect of interconnection topology, in general, the SPICE-based simulation is necessary.…”

Section: Introductionmentioning

confidence: 99%

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects

Chun

Kim

Kang

2007

16th Asian Test Symposium (ATS 2007)

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Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICEbased pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

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Test pattern generation for signal integrity faults on long interconnects

Abstract: Abstract

Cited by 30 publications

References 27 publications

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects

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