Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

Lee, Sang Ho; Park, Jin; Kim, Geon Uk; Kang, Ga Eon; Heo, Jun; Jeon, So Ra; Yoon, Young Jun; Seo, Jae Hwa; Jang, Jaewon; Bae, Jin‐Hyuk; Lee, Sin‐Hyung; Kang, In Man

doi:10.35848/1347-4065/acaca9

Cited by 4 publications

(3 citation statements)

References 30 publications

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“…The RSD is the percentage of SD divided by the mean, which was applied to compare changes in transfer characteristics and memory performance with different units of measurement and means. 36,37) Results indicate that the LER changes the transfer characteristics, particularly V th and I off .…”

Section: Effect Of Lermentioning

confidence: 99%

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

Kim,

Lee,

Park

et al. 2024

Jpn. J. Appl. Phys.

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In this study, a bulk fin-type field-effect transistor (FinFET)–based capacitorless one-transistor dynamic random-access memory (1T-DRAM) was proposed. The fabrication process of the proposed 1T-DRAM was similar to that of a typical junctionless bulk FinFETs, except that the p-type doped body fin region operated as a charge storage region. The effects of the geometrical variations, such as the fin angle (θfin) variation and line edge roughness (LER), which are inevitable in fabrication, on the transfer characteristics and memory performance of the proposed 1T-DRAM were studied. θfin was varied from 90° to 80°, and 200 samples with the LER were analyzed. Results revealed that the transfer characteristics and memory performance were affected by geometrical variations. However, the proposed 1T-DRAM exhibited an excellent retention time in all cases because the charge storage region was separated from the region of operation.

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Section: Effect Of Lermentioning

confidence: 99%

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

Kim,

Lee,

Park

et al. 2024

Jpn. J. Appl. Phys.

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“…To overcome this issue, various methods and structures have been studied. [12][13][14][15][16][17][18][19][20][21] However, the SOI technology is highly expensive and involves a complex fabrication process. Polycrystalline silicon (poly-Si) has been proposed as a low-cost alternative to develop SOI-like structures.…”

Section: Introductionmentioning

confidence: 99%

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

Bae,

Lee,

Park

et al. 2024

Jpn. J. Appl. Phys.

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (poly-Si) with a vertical underlap structure and a separated channel layer was designed and analyzed. The memory performance was improved by the vertical underlap structure and the region separated into channel and storage layers. The vertical underlap structure suppressed the recombination rate by storing the holes in the isolated body and could be more easily fabricated than a conventional underlap structure. The thicknesses of the vertical underlap structure and storage region were optimized to enhance the memory performance. When the grain boundary (GB) is centrally located, the proposed 1T-DRAM demonstrates a retention time and sensing margin of 3.618 s and 29.93 μA μm−1, respectively. Even when the GB is in the worst position at T = 358 K, the memory still shows a retention time of 1.991 s and a sensing margin of 4.51 μA μm−1.

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“…As a result, the capacitor aspect ratio of the conventional 1T-1C DRAM is limited. To solve this problem, one-capacitor DRAMs (1T-DRAM) without a capacitor are attracting attention [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 ]. The 1T-DRAM consists of one transistor without a capacitor and uses a partially definite floating body area on the Silicon-on-Insulator (SOI) substrate as a data storage region.…”

Section: Introductionmentioning

confidence: 99%

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

et al. 2023

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

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Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

Cited by 4 publications

References 30 publications

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

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