Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

Gundapaneni, Suresh; Ganguly, Swaroop; Kottantharayil, Anil

doi:10.1109/led.2010.2099204

Cited by 216 publications

(79 citation statements)

References 7 publications

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“…may be used as sidewall spacer layers in nanoscale MOSFETs as they have pretty high dielectric constant, acceptable amount of conduction and valence band offsets with Si and also are thermodynamically stable with Si [9,10]. There have been many reports regarding the impact of various single high-k sidewall spacer layers on the logic and analog/RF performance of MOSFETs [5,8,11,12]. The source/drain resistance plays an important role in determining the characteristics of MOSFETs particularly at the nanodecameter technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Roy

Biswas

2016

Superlattices and Microstructures

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Section: Introductionmentioning

confidence: 99%

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Roy

Biswas

2016

Superlattices and Microstructures

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“…Firstly, its fabrication process would be easier than the conventional MOSFETs as the intricate doping process for source and drain is avoided. Secondly, the electric field in the ON-state of the device is low [3]. Thirdly, the mobility in JLFET is improved and insensitive to the interface of gate oxide to channel due to its bulk conduction, unlike surface conduction in the inversion mode device, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…A number of JLFET structures have been proposed with variations in topologies, such as single gate bulk planar JLFET [3], single gate silicon-on-insulator (SOI) JLFET [4], multi-gate nanowire junctionless transistors [5], gate-all-around nanowire junctionless transistors [6], as well as junctionless tunnel FET [7]. However, little attention is given on the gate materials in JLFET as well as the processing sequence on the gate.…”

Section: Introductionmentioning

confidence: 99%

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

Riyadi¹,

Sukawati²,

Prakoso³

et al. 2016

IJECE

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The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.

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“…Thus, the junctionless transistor (JLT) without counter-doped metallurgical junctions has been proposed [5][6][7][8][9]. In comparison with the conventional MOSFETs, the JLT features a single-doping species at the same concentration in its source, drain, and channel.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Kim¹,

Seo²,

Yoon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulktype fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (W fin ) and height (H fin ) of the fin as well as the channel doping concentration (N ch ). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.Index Terms-Junctionless, fin-shaped field-effect transistor (FinFET), short-channel effect (SCE), 3-D device simulation

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Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

Cited by 216 publications

References 7 publications

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

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