Buri

Zhao, Jishen; Li, Sheng; Chang, Jichuan; Byrne, John; Ramírez, Laura; Lim, Kevin; Xie, Yuan; Faraboschi, Paolo

doi:10.1145/2808233

Cited by 25 publications

(1 citation statement)

References 34 publications

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“…An overflow scenario is not possible in MBZip. In Buri [49], the authors propose a hardware technique to manage allocation/reallocation of compressed pages. The OS support required is minimal.…”

Section: Related Workmentioning

confidence: 99%

MBZip

Raghavendra

Panda

Mutyam

2017

ACM Trans. Archit. Code Optim.

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Compression techniques at the last-level cache and the DRAM play an important role in improving system performance by increasing their effective capacities. A compressed block in DRAM also reduces the transfer time over the memory bus to the caches, reducing the latency of a LLC cache miss. Usually, compression is achieved by exploiting data patterns present within a block. But applications can exhibit data locality that spread across multiple consecutive data blocks. We observe that there is significant opportunity available for compressing multiple consecutive data blocks into one single block, both at the LLC and DRAM. Our studies using 21 SPEC CPU applications show that, at the LLC, around 25% (on average) of the cache blocks can be compressed into one single cache block when grouped together in groups of 2 to 8 blocks. In DRAM, more than 30% of the columns residing in a single DRAM page can be compressed into one DRAM column, when grouped together in groups of 2 to 6. Motivated by these observations, we propose a mechanism, namely, MBZip, that compresses multiple data blocks into one single block (called a zipped block), both at the LLC and DRAM. At the cache, MBZip includes a simple tag structure to index into these zipped cache blocks and the indexing does not incur any redirectional delay. At the DRAM, MBZip does not need any changes to the address computation logic and works seamlessly with the conventional/existing logic. MBZip is a synergistic mechanism that coordinates these zipped blocks at the LLC and DRAM. Further, we also explore silent writes at the DRAM and show that certain writes need not access the memory when blocks are zipped. MBZip improves the system performance by 21.9%, with a maximum of 90.3% on a 4-core system.

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Section: Related Workmentioning

confidence: 99%

MBZip

Raghavendra

Panda

Mutyam

2017

ACM Trans. Archit. Code Optim.

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A low‐latency memory‐cube network with dual diagonal mesh topology and bypassed pipelines

Oda,

Keida,

Yasudo

2024

Concurrency and Computation

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SummaryA memory cube network is an interconnection network composed of 3D stacked memories called memory cubes. By exploiting a packet switching, it can provide fast memory accesses to a large number of memory cubes. Although interconnection networks have been studied in many years for supercomputers and data centers, existing technologies are difficult to apply to memory cube networks. This is because the link length and the number of ports are limited, and hence the hop count increases. In this article, we propose a dual diagonal mesh (DDM), a layout‐oriented memory‐cube network. Furthermore, we propose the routing algorithm and the router architecture with bypassed pipelines for DDM. Our experimental results demonstrate that our routing and router architecture with bypassed pipelines reduces the memory access latency. We implement four router architectures and evaluate them with the traffic patterns derived from the NAS parallel benchmark.

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Storage technologies and their data

Thomasian¹

2022

Storage Systems

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Buri

Cited by 25 publications

References 34 publications

MBZip

MBZip

A low‐latency memory‐cube network with dual diagonal mesh topology and bypassed pipelines

Storage technologies and their data

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