Buried Bitline for sub-5nm SRAM Design

Mathur, Rahul; Bhargava, Mudit; Salahuddin, Shairfe Muhammad; Schuddinck, P.; Ryckaert, Julien; Annamalai, S. J. K.; Gupta, Anshul; Chong, YK; Sinha, Saurahb; Cline, Brian; Kulkarni, Jaydeep P.

doi:10.1109/iedm13553.2020.9372042

Cited by 4 publications

(4 citation statements)

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“…7 shows the two resistances (RBL and RWL) and three capacitances (CBL, CWL, and CQ) that have the most significant impact on the SRAM performance. Interconnect RC values were similar to previous studies, and it could be confirmed that extracted RC were within a reasonable range [16]. Generally, RBL and RWL changed in proportion to cell width and height length (Fig.…”

Section: B M3d Sram Structures: Area and Parasitic Rcsupporting

confidence: 88%

“…The reason is, in the sub-3-nm node, a metal line had immense resistances due to the small electrical area with surface and grain boundary scattering (the worst case) [15]. However, since various SRAM assist circuit techniques [16] and methods for lowering the resistivity of BEOL materials [17] were being studied, it was necessary to analyze even the low resistance one (the ideal case).…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…The minimum gap between metals was set to 12 nm, and the SRAM array size was set to 256 by 256. The width of the word line (WL) and metal line 2 (M2) were set large to mitigate the inevitable large array resistance [16]. In M3D, there is a problem with active sheet resistance due to the post-annealing of the bottom device.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

et al. 2021

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For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM3D). SRAM3D could not directly connect the top-tier device and the bottom-tier metal line. Thus two tiers had to be connected by bypassing the metal line. As a result, SRAM3D wasted the area to place the monolithic interlayer via and did not get 50 % area scaling. However, gate and S/D bottom contact schemes, GBC and SDBC, could solve these problems. Although these methods required additional process steps, they brought significant advantages in interconnect RC and PPA. Based on a 26 nm width nanosheet transistor, SRAM3D showed a 30 % area reduction compared to 2D SRAM (SRAM2D), whereas SRAMSDGBC showed a 50 % area reduction. In the ideal (worst) case which ignoring (considering) the array resistance, the read and write access time of SRAMSDGBC were improved 7.7 % (19 %) and 8.3 % (33 %) than SRAM3D, and the write dynamic power was improved by 5.9 % (5 %). Especially, SRAMSDGBC showed improved PPA in the worst case compared to SRAM2D_Cu, which had relatively small interconnect resistivity. Namely, GBC and SDBC schemes are essential to enhance the PPA of M3D cells and will be a promising scheme in M3D SRAM and other logic cells.

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Section: B M3d Sram Structures: Area and Parasitic Rcsupporting

confidence: 88%

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

et al. 2021

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“…MRRs enabling random access functionality. This, in turn, leads to the construction of optical SRAM with striking functional similarities to electrical SRAMs, including complementary data storage and differential read-out of data 18 . Furthermore, the proposed optical-SRAM (O-SRAM) can be arranged in an array-like fashion for creating large-scale on-chip optical storage.…”

mentioning

confidence: 99%