Electric-field manipulation of ferromagnetism has the potential for developing a new generation of electric devices to resolve the power consumption and variability issues in today's microelectronics industry. Among various dilute magnetic semiconductors (DMSs), group IV elements such as Si and Ge are the ideal material candidates because of their excellent compatibility with the conventional complementary metal-oxide-semiconductor (MOS) technology. Here we report, for the first time, the successful synthesis of self-assembled dilute magnetic Mn(0.05)Ge(0.95) quantum dots with ferromagnetic order above room temperature, and the demonstration of electric-field control of ferromagnetism in MOS ferromagnetic capacitors up to 100 K. We found that by applying electric fields to a MOS gate structure, the ferromagnetism of the channel layer can be effectively modulated through the change of hole concentration inside the quantum dots. Our results are fundamentally important in the understanding and to the realization of high-efficiency Ge-based spin field-effect transistors.

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Magnetically doped Si and Ge nanowires have potential application in future nanowire spin-based devices. Here, we report a supercritical fluid method for producing single crystalline Mn-doped Ge nanowires with a Mn-doping concentration of between 0.5-1.0 atomic % that display ferromagnetism above 300 K and a superior performance with respect to the hole mobility of around 340 cm(2)/Vs, demonstrating the potential of using these nanowires as building blocks for electronic devices.

Operation parameters of magnetic quantum cellular automata are evaluated for the purposes of reliable logic operation. The dynamics of the nanomagnets is simulated via the Landau-Lifshitz-Gilbert equations with a stochastic magnetic field corresponding to thermal fluctuations. It is found that in the macrospin approximation the switching speed does not change under scaling of both size and distances between nanomagnets. Thermal fluctuations put a limitation on the size of nanomagnets, since the gate error rate becomes excessive for nanomagnets smaller than 200nm at room temperature.

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.