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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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In this letter, a postgate CF4-plasma treatment is proposed and demonstrated on germanium (Ge) metal-oxide-semiconductor capacitors and the effects of fluorine (F) incorporation have been studied on both high-k∕Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k∕Ge interface. Electrical characteristics such as frequency dispersion, interface state density (Dit), and gate leakage are improved after F incorporation. Interface quality of high-k∕Ge gate stack is further improved by combining Si surface passivation and postgate CF4 treatment, with its Dit as low as 4.85×1011cm−2eV−1.