Buried Interfaces in Halide Perovskite Photovoltaics

Abstract

Understanding the fundamental properties of buried interfaces in perovskite photovoltaics is of paramount importance to the enhancement of device efficiency and stability. Nevertheless, accessing buried interfaces poses a sizeable challenge because of their non‐exposed feature. Herein, the mystery of the buried interface in full device stacks is deciphered by combining advanced in situ spectroscopy techniques with a facile lift‐off strategy. By establishing the microstructure–property relations, the basic losses at the contact interfaces are systematically presented, and it is found that the buried interface losses induced by both the sub‐microscale extended imperfections and lead‐halide inhomogeneities are major roadblocks toward improvement of device performance. The losses can be considerably mitigated by the use of a passivation‐molecule‐assisted microstructural reconstruction, which unlocks the full potential for improving device performance. The findings open a new avenue to understanding performance losses and thus the design of new passivation strategies to remove imperfections at the top surfaces and buried interfaces of perovskite photovoltaics, resulting in substantial enhancement in device performance.

Universal Bottom Contact Modification with Diverse 2D Spacers for High‐Performance Inverted Perovskite Solar Cells

“…Lift-Off Process: The lift-off process was in the same way as Zhu et al reported. [63] Firstly, the PTAA (30 mg mL -1 , in toluene) solution was spincoated onto the pre-cleaned ITO at 4000 rpm for 40 s and annealed at 100 °C for 15 min in a N 2 -filled glovebox. The PTAA layer in the lift-off process serves as a sacrificial layer.…”

High‐Performance ITO‐Free Perovskite Solar Cells Enabled by Single‐Walled Carbon Nanotube Films

“…To ensure accuracy, a mask with an aperture area of 0.09 cm 2 was employed during the measuring process. [ 80,81 ] The data were collected by the IV testing system with software (IVS‐KA5000). The stabilized power output was measured at the maximum power output bias voltage.…”

Switched‐On: Progress, Challenges, and Opportunities in Metal Halide Perovskite Transistors

“…[ 89 ] The microstructure can also influence phase transitions, [ 90 ] thus affecting the temperature‐dependence of the FET properties. An important note is that the microstructure at the surface might vary from that at the bottom interface with the substrate – evident for example by scanning electron microscopy (SEM) [ 91 ] – which leads to different performance of the same film in different FET device architectures.…”

“…Defect management in this case is far more complex, considering the buried nature of that interface and the difficulty to not only modify it, but also to characterize it. [ 91 ] One possible solution could be based on the integration of passivating agents onto the substrate, prior to the deposition of the perovskite layer. [ 251 ] Alternatively, guided vertical segregation of the passivating additive towards the substrate during deposition of the perovskite precursor solution may also result in a well passivated bottom interface.…”