Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V<sub>th</sub> tuning and RF shielding applications

Vandooren, A.; Wu, Z.; Khaled, Ahmad; Franco, J.; Parvais, B.; Li, W.; Witters, L.; Walke, A.; Peng, Lan; Rassoul, Nouredine; Matagne, P.; Debruyn, Haroen; Jamieson, Geraldine; Inoue, Fumihiro; Devriendt, K.; Teugels, Lieve; Heylen, N.; Vecchio, E.; Zheng, T.; Radisic, Dunja; Rosseel, Eveline; Vanherle, W.; Hikavyy, Andriy; Chan, B. T.; Besnard, G.; Schwarzenbach, W.; Gaudin, G.; Radu, Ionut; Nguyen, B.-Y.; Waldron, Niamh; Heyn, V. De; Demuynck, S.; Boemmels, J.; Ryckaert, Julien; Collaert, N.; Mocuta, D.

doi:10.23919/vlsit.2019.8776490

Cited by 7 publications

(5 citation statements)

References 1 publication

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“…Recent studies [22,23] have demonstrated efficient decoupling solutions between sensitive tiers in 3DSI via the process integration of a conductive layer, i.e., an inter-tier Ground Plane (GP).…”

Section: Inter-tier Ground Plane Necessitymentioning

confidence: 99%

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

et al. 2022

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In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a Back-Side Illuminated, 4T–APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.

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Section: Inter-tier Ground Plane Necessitymentioning

confidence: 99%

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

et al. 2022

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“…For this purpose, as drawn schematically in Fig. 7, the two bias schemes introduced in Section I are deployed, which aim to mimic both dynamic and static back-gate biasing scheme adopted in FDSOI devices [7,8,15]. For the "constant VG" scheme, a non-zero back-gate bias is applied only during stress stage (i.e.…”

Section: Bti Reliabilitymentioning

confidence: 99%

“…They are also particularly suitable to enable a top tier device fabrication at low thermal budgets, as their uniform channel doping can be activated (at high temperature) before transferring and bonding the top silicon slab on top of a prefabricated CMOS bottom tier [3]. Thanks to the flexibility of 3D sequential integration, a metal back-gate can be easily integrated with junction-less top-tier devices to enable various biasing schemes, such as dynamic or static back-gate biasing [7,8], to optimize the powerperformance trade-off for different applications.…”

Section: Introductionmentioning

confidence: 99%

“…Before bonding of the donor wafer on top of the processed bottom-tier carrier wafer, a BOX layer composed of 10nm RTO and a 10nm (or 20nm) PEALD oxide is deposited, followed by a 50nm PECVD TiN metal layer, which serves as the back-gate. Details of this 3D sequential integration flow can be found in [7,11]. Two silicon channel thickness (Tsi=10/15 nm) and two buried oxide thickness (BOX=20/30nm), resulting in 4 variants of toptier p/n FETs are investigated in this work.…”

Section: Introductionmentioning

confidence: 99%

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Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Franco

Vandooren

et al. 2021

IEEE Trans. Electron Devices

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Low thermal budget junction-less transistors with backgate are fabricated as top-tier devices for 3D sequential integration. The impact of back-gate bias on carrier mobility and BTI reliability are investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias, which is ascribed to the carrier re-distribution from the frontgate interface towards back-gate interface. Regarding BTI reliability, if a back-gate bias (VBG) is applied only during on-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox). Therefore, supplying a forward backgate bias during on-state can be used to adjust device performanceas VBG modulates the channel current through Vth and mobilitywithout reliability penalty. On the other hand, if the back-gate bias is applied during both on-and off-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG-Vth(VBG) is kept constant under different VBG's], the BTI reliability can be improved under forward back-gate bias (due to a reduced Eox in the frontgate) without performance loss. The latter property can be used to improve the device reliability under circuit operation.

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“…Recent studies [14], [15] have examined the feasibility of integrating an inter-tier Ground plane in 3DSI that can act as an efficient decoupling layer between sensitive tiers. The necessity for an inter-tier Ground Plane integration results from the specifications targeted for each application and is eventually a trade-off between the process complexity and the inter-tier coupling sensitivity.…”

Section: Inter-tier Ground Plane Necessitymentioning

confidence: 99%

Inter-tier Coupling Analysis in Back-illuminated Monolithic 3DSI Image Sensor Pixels

Sideris

Peizerat

Batude

et al. 2021

2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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This study investigates the inter-tier coupling, for a Back-Side Illuminated (BSI) 4-Transistor (4T) pixel with its diode and Transfer Gate on the bottom tier and the rest of its circuitry on the top tier of a 3D Sequential Integration (3DSI) process. Variations due to coupling are compared with variations due to temperature, showing that both effects may result in a readout error of the same order of magnitude for the top-tier readout circuit. Nevertheless, we demonstrate that in a typical rolling readout, the sequence of the pixel control signals makes the coupling effect nearly negligible. As a result, we suggest that the fabrication of an inter-tier ground plane for electrical isolation is not strictly necessary for Monolithic 3D pixels when the readout top tier is directly stacked on the photodiode bottom tier.

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Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications

Cited by 7 publications

References 1 publication

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Inter-tier Coupling Analysis in Back-illuminated Monolithic 3DSI Image Sensor Pixels

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Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

Cited by 7 publications

References 1 publication

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel

Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Inter-tier Coupling Analysis in Back-illuminated Monolithic 3DSI Image Sensor Pixels

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Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications