Abstract:Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating programs.This paper explores a complementary approach that attacks the source (poor reference locality) of the problem rather than its manifestation (memory latency). It demonstrates that careful data organization and layout provides an essential mechanism to improv… Show more
“…implemented cache specific techniques such as compression and line coloring for LDS nodes in a memory allocator [3] and a generational garbage collector [4]. One of the earliest software-controlled LDS prefetching scheme was SPAID of Lipasti et.…”
“…implemented cache specific techniques such as compression and line coloring for LDS nodes in a memory allocator [3] and a generational garbage collector [4]. One of the earliest software-controlled LDS prefetching scheme was SPAID of Lipasti et.…”
“…Chilimbi et al discusses making pointerbased data structures cache-conscious in [8]. They focus on providing structure layouts to make tree structures cache-conscious.…”
Section: Related Workmentioning
confidence: 99%
“…A number of groups are attempting to improve performance by performing computations in memory [6] [25]. Other groups are attacking the problem in software; either in the compiler through reordering instructions and prefetching [18] [19][20] [36] or through complex data layouts to improve cache performance [8][10] [15].…”
“…Cache conscious data placement has been explored in [4,5,9]. The technique tries to pack LDS nodes that are accessed in a row into the same or consecutive cache blocks.…”
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