Effective jump-pointer prefetching for linked data structures

Roth, Aaron; Sohi, Gurindar S.

doi:10.1109/isca.1999.765944

Cited by 67 publications

(24 citation statements)

References 18 publications

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“…Researchers have proposed different techniques to hide the long memory access latency, such as software prefetching [4,5,6,7] and hardware prefetching [8,9,10,11,12]. In software prefetching, the compiler inserts prefetch instructions that bring the indicated block of data onto onchip memory.…”

Section: Related Workmentioning

confidence: 99%

Template-based memory access engine for accelerators in SoCs

Fang

Iyer

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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With the rapid progress in semiconductor technologies, more and more accelerators can be integrated onto a single SoC chip. In SoCs, accelerators often require deterministic data access. However, as more and more applications are running simultaneous, latency can vary significantly due to contention. To address this problem, we propose a template-based memory access engine (MAE) for accelerators in SoCs. The proposed MAE can handle several common memory access patterns observed for near-future accelerators. Our evaluation results show that the proposed MAE can significantly reduce memory access latency and jitter, thus very effective for accelerators in SoCs.

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Section: Related Workmentioning

confidence: 99%

Template-based memory access engine for accelerators in SoCs

Fang

Iyer

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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“…Their approaches, however, do not solve prefetching for general pointer-chasing codes. The jump-pointer approach [21] requires whole program analysis which may not be possible at compile time. Cahoon and McKinley try to detect the regularity of the memory stream at compile time for Java applications [3].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a compiler framework for helper threading on multi-core processors

Song

Kalogeropulos

Tirumalai

2005

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)

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Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes in parallel with the main thread that it attempts to accelerate. In this paper, the helper thread merely prefetches data into a shared cache and does not incur any other programmer visible effects. Helper thread prefetching has been proposed as a viable solution in various scenarios where it is difficult to prefetch efficiently within the main thread itself. This paper presents our helper threading experience on SUN's second dual-core SPARC microprocessor, the UltraSPARC IV+. The two cores on this processor share an on-chip L2 and an off-chip L3 cache. We present a compiler framework to automatically construct helper threads and evaluate our scheme on the UltraSPARC IV+ processor. Our preliminary results using helper threads on the SPEC CPU2000 suite show gains of up to 22% on programs that suffer substantial L2 cache misses while at the same time incurring negligible losses on programs that do not suffer L2 cache misses.

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“…Prefetching for pointer chasing references and indirect memory references [23][25] [29][35] [22] are relatively challenging since they incur a higher overhead, and must be used more carefully. A typical compiler would not attempt high overhead prefetching unless there is sufficient evidence that a code region has frequent data cache misses.…”

Section: Impact Of Micro-architectural Constraintsmentioning

confidence: 99%

“…Santhanam et al discussed the major implementation issues of compile time prefetching on a particular RISC processor: HP-PA8000 [30]. Jump Pointer [29], which has been used widely to break the serial LDS (linked data structure) traversal, stores pointers several iterations ahead in the node currently visited. Other research tried to improve spatial locality and runtime memory reference efficiency with improved compilation methods.…”

Section: Software Prefetchingmentioning

confidence: 99%

The performance of runtime data cache prefetching in a dynamic optimization system

Lu¹,

Chen²,

Fu³

et al.

22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)

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Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we implement runtime data cache prefetching in the dynamic optimization system ADORE (ADaptive Object code REoptimization). Its performance has been compared with static software prefetching on the SPEC2000 benchmark suite. Runtime cache prefetching shows better performance. On an Itanium 2 based Linux workstation, it can increase performance by more than 20% over static prefetching on some benchmarks. For benchmarks that do not benefit from prefetching, the runtime optimization system adds only 1%-2% overhead. We have also collected cache miss profiles to guide static data cache prefetching in the ORC R compiler. With that information the compiler can effectively avoid generating prefetches for loops that hit well in the data cache.

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Effective jump-pointer prefetching for linked data structures

Abstract: Current techniques for prefetching linked data structures (LDS)

Cited by 67 publications

References 18 publications

Template-based memory access engine for accelerators in SoCs

Template-based memory access engine for accelerators in SoCs

Design and implementation of a compiler framework for helper threading on multi-core processors

The performance of runtime data cache prefetching in a dynamic optimization system

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