16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) 2011
DOI: 10.1109/aspdac.2011.5722175
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Template-based memory access engine for accelerators in SoCs

Abstract: With the rapid progress in semiconductor technologies, more and more accelerators can be integrated onto a single SoC chip. In SoCs, accelerators often require deterministic data access. However, as more and more applications are running simultaneous, latency can vary significantly due to contention. To address this problem, we propose a template-based memory access engine (MAE) for accelerators in SoCs. The proposed MAE can handle several common memory access patterns observed for near-future accelerators. Ou… Show more

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Cited by 5 publications
(8 citation statements)
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“…Otherwise, we must create identical copies of the data in the write blocks (P b = W b × |L b |), each with capacity C PB = Height, as shown in the lower part of Fig. 5; in this way, each memoryread interface is assigned to a distinct parallel block and is guaranteed to access the data without conflicts [9] as long as the corresponding memory-write operations create consistent copies of the data in each bank.…”
Section: System-level Memory Optimizationmentioning
confidence: 99%
See 2 more Smart Citations
“…Otherwise, we must create identical copies of the data in the write blocks (P b = W b × |L b |), each with capacity C PB = Height, as shown in the lower part of Fig. 5; in this way, each memoryread interface is assigned to a distinct parallel block and is guaranteed to access the data without conflicts [9] as long as the corresponding memory-write operations create consistent copies of the data in each bank.…”
Section: System-level Memory Optimizationmentioning
confidence: 99%
“…This determines the maximum number of parallel blocks and, thus, the minimum number of banks that are required to provide this bandwidth (lines 3-5). We also determine an initial size for these banks based on the data allocation strategy to be implemented (lines [6][7][8][9].…”
Section: Global Transformations 1) Definition Of Memory Subsystemmentioning
confidence: 99%
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“…However, before this paper, there has been no comprehensive analysis of the effects of multiple accelerators processing concurrently large amounts of data accessed through off-chip memory. The effects of multiple accelerators accessing the same memory controller has been studied before as part of a work that proposes a configurable module to manage many access patterns [17]. This module, however, is tightly coupled with the controller and the extension to multiple memory controllers is not straightforward.…”
Section: Related Workmentioning
confidence: 99%
“…Architectural solutions for heterogeneous architectures are usually evaluated by simulation [8,17,21]. However, as the complexity of these architectures increases, this approach is becoming unfeasible.…”
Section: Related Workmentioning
confidence: 99%