Cache-Hierarchy Contention-Aware Scheduling in CMPs

Abstract

Abstract-In order to improve CMP performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multi-level cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, contention points may appear along the whole memory hierarchy. Moreover, this problem is expected to aggravate in future technologies, since the number of cores and hardware threads, and consequently the size of the shared caches increases with each microprocessor generation. This paper characterizes the impact on performance of the different contention points that appear along the memory subsystem. The analysis shows that some benchmarks are more sensitive to contention in higher levels of the memory hierarchy (e.g., shared L2) than to main memory contention. In this paper we propose two generic scheduling strategies for CMPs. The first strategy takes into account the available bandwidth at each level of the cache hierarchy. The strategy selects the processes to be co-scheduled and allocates them to cores in order to minimize contention effects. The second strategy also considers the performance degradation each process suffers due to contention aware scheduling. Both proposals have been implemented and evaluated in a commercial single-threaded quad-core processor with a relatively small two-level cache hierarchy. The proposals reach, on average, a performance improvement by 5.38% and 6.64% when compared with the Linux scheduler while this improvement is by 3.61% for an state-of-the-art memory-contention aware scheduler under the evaluated mixes.

Bandwidth-Aware On-Line Scheduling in SMT Multicores

“…More recent scheduling strategies consider several levels of the memory hierarchy. Feliu et al [6], [11] addressed bandwidth contention along the memory hierarchy of CMPs.…”

“…The microbenchmark is designed to minimize the cache space contention, distributing the accesses among all the cache sets, so that the measured performance degradation is caused by bandwidth contention [11]. The performance degradation that each benchmark suffers is analyzed when it runs concurrently with one and five instances of the designed microbenchmark, respectively.…”

Addressing Fairness in SMT Multicores with a Progress-Aware Scheduler

“…To mimic the Linux behavior from this user-level scheduler, all the processes are allowed to run each quantum on any core, so the Linux kernel scheduler must determine the actual co-schedule (both process selection and allocation) [10], [11].…”

“…Contention in shared resources has been addressed in scheduling algorithms, but an important piece of this work in the past [11], [10], [16], [9] mainly focus on performance without taking fairness into account. This paper is mainly related to two research topics: fairness techniques and performance predictability.…”

Contention-Aware Scheduling for SMT Multicore Processors

“…However, targeting fairness and performance at the same time is not an easy task. For example, a prevalent approach to improve performance consists in balancing the memory requests of a multiprogram workload along its execution time [11] [12]. In contrast, to improve fairness, the processes with less accumulated progress should be prioritized over processes with superior progress.…”