CacheZoom: How SGX Amplifies the Power of Cache Attacks

Moghimi, Ahmad; Irazoqui, Gorka; Eisenbarth, Thomas

doi:10.1007/978-3-319-66787-4_4

Cited by 188 publications

(169 citation statements)

References 45 publications

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“…Despite the applicability of LLC attacks, attacks on coreprivate resources such as L1 cache are as important [23,35]. Attacks on SGX in a system level adversarial scenario are notable examples [20,36]. There are other shared resources, which can be utilized to construct timing channels [37].…”

Section: Related Workmentioning

confidence: 99%

“…Cache attacks can be exploited by adversaries where they share system cache memory with benign users. In scenarios where the adversary can colocate with a victim on the same core, she can attack core-private resources such as L1 cache, e.g., OS adversaries [20,36]. In cloud environment, virtualization platforms allow sharing of logical processors to different VMs; however, attacks on the shared LLC have a higher impact, since LLC is shared across all the cores.…”

Section: Cache Attacksmentioning

confidence: 99%

“…Both implementations have optimizations to hinder cache attacks. In fact, the AES implementation features a constant cache profile and can thus be considered resistant to most microarchitectural attacks including cache attacks and high-resolution attacks as described in [20]. MemJam can still extract the keys from both implementations due to the intra cache-line spatial resolution as depicted in Figure 5.…”

Section: Memjam Correlation Attackmentioning

confidence: 99%

“…Having said that, SGX must remain secure in the presence of malicious OS, thus modification of OS resources for facilitation of side-channel attacks is relevant and within the considered threat model. Previous works demonstrate high resolution attacks with 4 kB page [59,60] and 64 B cache line granularity [20,61]. Intel declared microarchitectural leakages out of scope for SGX, thus pushing the burden of writing leakage free constant-time code onto enclave developers.…”

Section: Memjaming Sgx Enclavementioning

confidence: 99%

“…Combining small tables with cache state normalization, i.e., loading all table entries into cache before each operation, defeats cache attacks in asynchronous mode, where the adversary is only able to perform one observation per operation. More advanced side channels such as exploitation of the thread scheduler [19], cache attack on interrupted execution of Intel Software Guard eXtension (SGX) [20], performance degradation [21] and leakage of other microarchitectural resources [22,23] remind us the importance of constant-time software implementations. One way to achieve constant-time memory behavior, is the adoption of small tables in combination with accessing all cache lines on each lookup [7].…”

Section: Introductionmentioning

confidence: 99%

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MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations

Moghimi¹,

Eisenbarth²,

Sunar³

2018

Int J Parallel Prog

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Cache attacks exploit memory access patterns of cryptographic implementations. Constant-Time implementation techniques have become an indispensable tool in fighting cache timing attacks. These techniques engineer the memory accesses of cryptographic operations to follow a uniform key independent pattern. However, the constant-time behavior is dependent on the underlying architecture, which can be highly complex and often incorporates unpublished features. CacheBleed attack targets cache bank conflicts and thereby invalidates the assumption that microarchitectural side-channel adversaries can only observe memory with cache line granularity. In this work, we propose MemJam, a side-channel attack that exploits false dependency of memory read-after-write and provides a high quality intra cache level timing channel. As a proof of concept, we demonstrate the first key recovery attacks on a constant-time implementation of AES, and a SM4 implementation with cache protection in the current Intel Integrated Performance Primitives (Intel IPP) cryptographic library. Further, we demonstrate the first intra cache level timing attack on SGX by reproducing the AES key recovery results on an enclave that performs encryption using the aforementioned constant-time implementation of AES. Our results show that we can not only use this side channel to efficiently attack memory dependent cryptographic operations but also to bypass proposed protections. Compared to CacheBleed, which is limited to older processor generations, MemJam is the first intra cache level attack applicable to all major Intel processors including the latest generations that support the SGX extension.

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