Calcium fluoride as high-k dielectric for 2D electronics

Wen, Chao; Lanza, Mario

doi:10.1063/5.0036987

Cited by 29 publications

(8 citation statements)

References 121 publications

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“…Among those explored candidates, the hexagonal boron nitride (h-BN) is the most widely used dielectric in building 2D FETs. , However, h-BN exhibits a relatively low dielectric constant (ε r ∼ 3.9), resulting in a weaker electrostatic control to the channel and a higher operation voltage than those of high-κ dielectrics. , Atomically thin 2D transition metal oxides (e.g., TiO 2 and others) have also been synthesized via liquid exfoliation or a direct oxidation process. − Although the obtained nanosheets exhibit large dielectric constants (ε r > 100), they usually have small sizes or lack crystallinity control. Recently, a mechanical exfoliation of 2D insulators from layered vdW crystals (e.g., α-MoO 3 and VOCl) , or a direct synthesis of large scale nonlayered high-κ 2D insulators/ionic crystals (e.g., antimony oxides and CaF 2 ) are also reported, − while a complete understanding of their properties is still at an early stage and requires more investigations.…”

Section: Introductionmentioning

confidence: 99%

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Liu

et al. 2022

ACS Appl. Mater. Interfaces

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The gate dielectric layer is an important component in building a field-effect transistor. Here, we report the synthesis of a layered rhombohedral-structured MnAl2S4 crystal, which can be mechanically exfoliated down to the monolayer limit. The dielectric properties of few-layered MnAl2S4 flakes are systematically investigated, whereby they exhibit a relative dielectric constant of over 6 and an electric breakdown field of around 3.9 MV/cm. The atomically smooth thin MnAl2S4 flakes are then applied as a dielectric top gate layer to realize a two-dimensional van der Waals stacked field-effect transistor, which uses MoS2 as a channel material. The fabricated transistor can be operated at a small drain–source voltage of 0.1 V and gate voltages within ranges of ±2 V, which exhibit a large on–off ratio over 107 at 0.5 V and a low subthreshold swing value of 80 mV/dec. Our work demonstrates that the few-layered MnAl2S4 can work as a dielectric layer to realize high-performance two-dimensional transistors, and thus broadens the research on high-κ 2D materials and may provide new opportunities in developing low-dimensional electronic devices with a low power consumption in the future.

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Section: Introductionmentioning

confidence: 99%

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Liu

et al. 2022

ACS Appl. Mater. Interfaces

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“…[115] As an insulator with a dielectric constant of 8.43 and a dielectric strength of 20.3 ± 0.9 MV cm −1 , CaF 2 can realize epitaxial growth of 2D channel materials on the surface and has good compatibility with 2D materials. [116] Mueller and co-workers fabricated CaF 2 with a thickness of ≈2 nm by MBE and constructed the FETs with the bottom CaF 2 gate by transferring CVD-grown MoS 2 . [115] Transmission electron microscopy (TEM) shows that CaF 2 and MoS 2 form an almost defect-free vdW interface, as shown in Figure 8b.…”

Section: D Dielectric/semiconductor Vdw Interfacesmentioning

confidence: 99%

Van der Waals‐Interface‐Dominated All‐2D Electronics

Zhang

et al. 2023

Advanced Materials

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The interface is the device. As the feature size rapidly shrinks, silicon‐based electronic devices are facing multiple challenges of material performance decrease and interface quality degradation. Ultrathin 2D materials are considered as potential candidates in future electronics by their atomically flat surfaces and excellent immunity to short‐channel effects. Moreover, due to naturally terminated surfaces and weak van der Waals (vdW) interactions between layers, 2D materials can be freely stacked without the lattice matching limit to form high‐quality heterostructure interfaces with arbitrary components and twist angles. Controlled interlayer band alignment and optimized interfacial carrier behavior allow all‐2D electronics based on 2D vdW interfaces to exhibit more comprehensive functionality and better performance. Especially, achieving the same computing capacity of multiple conventional devices with small footprint all‐2D devices is considered to be the key development direction of future electronics. Herein, the unique properties of all‐2D vdW interfaces and their construction methods are systematically reviewed and the main performance contributions of different vdW interfaces in 2D electronics are summarized, respectively. Finally, the recent progress and challenges for all‐2D vdW electronics are discussed, and how to improve the compatibility of 2D material devices with silicon‐based industrial technology is pointed out as a critical challenge.

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“…The performance of our dielectric materials versus existing dielectric materials is summarized in Figure 4d, from which we can see that our m-ZrO 2 shows superior performance. [11,12,14,15,[37][38][39][40]…”

Section: Dielectric Properties Of As-grown M-zromentioning

confidence: 99%

Controllable Oxidation of ZrS₂ to Prepare High‐κ, Single‐Crystal m‐ZrO₂ for 2D Electronics

et al. 2023

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High‐κ materials that exhibit large permittivity and band gaps are needed as gate dielectrics to enhance capacitance and prevent leakage current in downsized technology nodes. Among these, monoclinic ZrO2 (m‐ZrO2) shows good potential because of its inertness and high‐κ with respect to SiO2, but a method to produce ultrathin single crystal is lacking. Here, the controllable preparation of ultrathin m‐ZrO2 single crystals via the in situ thermal oxidation of ZrS2 is achieved. As‐grown m‐ZrO2 presents an equivalent oxide thickness of ≈0.29 nm, a high dielectric constant of ≈19, and a breakdown voltage (EBD) of ≈7.22 MV cm−1. MoS2 field effect transistor (FET) by using m‐ZrO2 as a dielectric layer shows comparable mobility to that using SiO2 dielectric. The ultraclean interface of m‐ZrO2/MoS2 and high crystalline quality of m‐ZrO2 lead to negligible hysteresis in transfer curves. Single crystal m‐ZrO2 dielectric shows potential application in digital complementary metal oxidesemiconductor (CMOS) logic FET.

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Calcium fluoride as high-k dielectric for 2D electronics

Cited by 29 publications

References 121 publications

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Van der Waals‐Interface‐Dominated All‐2D Electronics

Controllable Oxidation of ZrS₂ to Prepare High‐κ, Single‐Crystal m‐ZrO₂ for 2D Electronics

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Calcium fluoride as high-k dielectric for 2D electronics

Cited by 29 publications

References 121 publications

Few-Layered MnAl2S4 Dielectrics for High-Performance van der Waals Stacked Transistors

Few-Layered MnAl2S4 Dielectrics for High-Performance van der Waals Stacked Transistors

Van der Waals‐Interface‐Dominated All‐2D Electronics

Controllable Oxidation of ZrS2 to Prepare High‐κ, Single‐Crystal m‐ZrO2 for 2D Electronics

Contact Info

Product

Resources

About

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Few-Layered MnAl₂S₄ Dielectrics for High-Performance van der Waals Stacked Transistors

Controllable Oxidation of ZrS₂ to Prepare High‐κ, Single‐Crystal m‐ZrO₂ for 2D Electronics