Can We Efficiently Check Concurrent Programs Under Relaxed Memory Models in Maude?

Alrahman, Yehia Abd; Andrić, Marina; Beggiato, Alessandro; Lafuente, Alberto Lluch

doi:10.1007/978-3-319-12904-4_2

Cited by 5 publications

(5 citation statements)

References 51 publications

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“…We believe that the implementation of the strong and the weak semantics will be useful to verify program properties, e.g., via model checking. To do so, state-space reduction techniques (similar to the ones investigated by Alrahman et al when representing a TSO memory model in the Maude rewriting framework [4]) will be needed.…”

Section: Discussionmentioning

confidence: 99%

“…Alrahman et al formalize and represent a small calculus with a relaxed memory model (total-store order TSO) and with a fence and a wait operation for synchronization [4]. They provide an implementation in Maude (a rewriting-based executable framework that precedes K) and explore ways to battle the state-space explosion (for instance by making use of partial order reduction and finding appropriate abstractions).…”

Section: Related Workmentioning

confidence: 99%

“…Consider the sequence of assignments x := 1; y := 2 as an example. The first assignment "happens-before" the second (as they are in program order), but it does not mean the first instruction is actually "done" before the second 4 , and especially, it does not mean that the effect of the two writes become observable in the given order. For example, a compiler might choose to change the order of the two instructions or the processor may rearrange memory instructions so that their effect may not be visible in program order.…”

Section: Introductionmentioning

confidence: 99%

“…The relation was called happened-before in the original paper 4. Assuming that x and y are not aliases in the sense that they refer to the same or "overlapping" memory locations.…”

mentioning

confidence: 99%

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Operational Semantics of a Weak Memory Model with Channel Synchronization

2018

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A multitude of weak memory models exists supporting various types of relaxations and different synchronization primitives. On one hand, they must be lax enough to allow for hardware and compiler optimizations; on the other, the more lax the model, the harder it is to reason about programs. Though the right balance is up for debate, a memory model should provide what is known as the SC-DRF guarantee, meaning that data-race free programs behave in a sequentially consistent manner. In this work we present a weak memory model for a calculus inspired by Go. Thus, different from previous approaches, we focus on a memory model with buffered channel communication as the sole synchronization primitive. While memory models are often defined axiomatically where the notion of a program is abstracted away (often as a graph with memory events as nodes), we formalize our model via an operational semantics. This allows us to prove the SC-DRF guarantee using a standard simulation technique that highlights invariants and gives insight into the how the memory works. Finally, we provide a concrete implementation in K, a rewrite-based executable semantic framework, which allows us to derive an interpreter for the proposed language.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The relation was called happened-before in the original paper 4. Assuming that x and y are not aliases in the sense that they refer to the same or "overlapping" memory locations.…”

mentioning

confidence: 99%

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Operational Semantics of a Weak Memory Model with Channel Synchronization

2018

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“…Instances of this operator are parameterized by a function on instructions, which for convenience we call a memory model. 1 We use this foundation to explore theoretically significant memory models that underlie modern processors.…”

Section: Foundations Of Instruction Reorderingmentioning

confidence: 99%

Parallelized sequential composition, pipelines, and hardware weak memory models

Colvin

2021

Preprint

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Since the introduction of the CDC 6600 in 1965 and its "scoreboarding" technique processors have not (necessarily) executed instructions in program order. Programmers of highlevel code may sequence independent instructions in arbitrary order, and it is a matter of significant programming abstraction and computational efficiency that the processor can be relied upon to make sensible parallelizations/reorderings of low-level instructions to take advantage of, for instance, multiple arithmetic units. At the architectural level such reordering is typically implemented via a per-processor pipeline, into which instructions are fetched in order, but possibly committed out of order depending on local considerations, provided any reordering preserves sequential semantics from that processor's perspective. However, multiprocessing and multicore architectures, where several pipelines run in parallel, can expose these processor-level reorderings as unexpected, or "weak", behaviours. Such weak behaviours are hard to reason about, and (via speculative execution) underlie at least one class of widespread security vulnerability.In this paper we introduce a novel program operator, parallelized sequential composition, which can be instantiated with a function that controls the reordering of atomic instructions. The operator generalises both standard sequential composition and parallel composition, and when appropriately instantiated exhibits many of the weak behaviours of the well-known hardware weak memory models TSO, Release Consistency, ARM, and RISC-V. We show that the use of this program-level operator is equivalent to sequential execution with reordering via a pipeline. Encoding reordering as a programming language operator admits the application of established compositional techniques (such as Owicki-Gries) for reasoning about weak behaviours, and is convenient for abstractly expressing properties from the literature such as sequential consistency. The semantics and theory is encoded and verified in the Isabelle/HOL theorem prover, and we give an implementation of the pipeline semantics in the Maude rewriting engine and use it empirically to show conformance of the semantics against established models of ARM and RISC-V, and elucidate some stereotypical weak behaviours from the literature.

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Parallelized Sequential Composition and Hardware Weak Memory Models

Colvin

2021

Lecture Notes in Computer Science

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Can We Efficiently Check Concurrent Programs Under Relaxed Memory Models in Maude?

Cited by 5 publications

References 51 publications

Operational Semantics of a Weak Memory Model with Channel Synchronization

Operational Semantics of a Weak Memory Model with Channel Synchronization

Parallelized sequential composition, pipelines, and hardware weak memory models

Parallelized Sequential Composition and Hardware Weak Memory Models

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