Canonical representations of high-level decision diagrams

Karputkin, Anton; Ubar, Raimund; Raik, Jaan; Tombak, Mati

doi:10.3176/eng.2010.1.06

Cited by 11 publications

(3 citation statements)

References 25 publications

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“…High-level Decision Diagrams (HLDDs) [29,30] can be used as a uniform approach for extracting and solving the constraints (3) in test generation for the modules of microprocessors.…”

Section: High-level Decision Diagrams and Functional Testmentioning

confidence: 99%

“…To compare the results with state-of-the-art, the quality of tests is measured by single SAF cover, however, at the same time, we target broader class of faults than single SAF, considering structural logic level faults such as conditional SAF [27,28], bridging and multiple faults, as well as the functional fault classes used traditionally in memory testing. For formal high-level functional fault modeling and test generation we use the idea of representing the instruction set and architecture of the microprocessor in form of High-Level Decision-Diagrams (HLDD) [29,30]. The HLDDs can be used as well for trading off different test characteristics such as test length, test generation time and fault coverage.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults(SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.

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“…High-level Decision Diagrams (HLDDs) [29,30] can be used as a uniform approach for extracting and solving the constraints (3) in test generation for the modules of microprocessors.…”

Section: High-level Decision Diagrams and Functional Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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“…We propose a formal method to automate the test program generation for microprocessors using high-level decision diagrams (HLDD) [14,15] as a diagnostic model. The novelties of the approach are: reduced probability of fault masking, better diagnostic opportunities, and compactness of the whole test thanks to uniform organization of test routines.…”

Section: A Jasnetski Et Al: Self-test Generation For Microprocessorsmentioning

confidence: 99%

Software-based self-test generation for microprocessors with high-level decision diagrams

Jasnetski¹,

Ubar²,

Tsertov³

et al. 2014

Proc. Estonian Acad. Sci.

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This paper presents a novel approach to automated behavioural level test program generation for microprocessors using the model of high-level decision diagrams (HLDD) for representing instruction sets. The methodology of using HLDDs for modelling of microprocessors, and a new HLDD-based fault model are developed. The procedures for automated test program generation are presented using a formal model of HLDDs. The feasibility and efficiency of the new methodology are demonstrated by carrying out experimental research on test generation for a 8-bit microprocessor. The results are promising, showing the advantages of the new method and demonstrating better quality of tests compared to previous results. A. Jasnetski et al.: Self-test generation for microprocessors49 test program generation method, which must comply with the high-quality fault coverage standards imposed by the industry.In general, the development of the SBST program consists of four steps: 1) creation and optimization of test pattern delivery templates in assembly language, 2) module-level instruction imposed (functional) constraint extraction, 3) test generation process for each module of the processor under test, 4) translation of test patterns to self-test programs.The last step is basically a process of joining the test pattern with the test pattern delivery template. Initial focus of the research was on the fault coverage of the tests. The fault coverage of the SBST test is primarily affected by the test patterns. One of the ways to obtain test patterns is to run ATPG. In [5] it was shown that the processor can be divided into modules under tests (MUTs) to ease the task of ATPG. The other way is to use random test patterns for MUTs [6]. Although the gate level fault coverage for MUT is acceptable in deterministic and random test pattern generation, some of the generated patterns are typically functionally infeasible when considering the processor as a whole. The latter requires a manual effort to collect the constraints that guide ATPG at gate level. Obviously, considering todays complexity of the gate level processor implementation it is not feasible to have manual operations at the gate level.An automatic constraint extraction, based on the gate level simulation of generated tests to check their functional feasibility, was proposed in [7]. But the efficiency of the method on the industrial processors was known to be low. In [8] it is suggested to shift test pattern generation from the gate level to the RT level. This is achieved by the reuse of the verification test patterns. The drawback of this method is that high fault coverage for structural faults cannot be guaranteed by verification test patterns.Considering the drawbacks of the previously mentioned methods we followed the idea to benefit from the test generation at gate level and to collect functional constraints at RT level description of the processor. One of the papers [9] shows the possibility to use the bounded model checker (BMC) to map the pregenerated test patterns into delivery ...

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