Capacitance modeling of gate material engineered cylindrical/surrounded gate MOSFETs for sensor applications

Verma, Jay Hind Kumar; Pratap, Yogesh; Haldar, Subhasis; Gupta, Radhey S.; Gupta, Mridula

doi:10.1016/j.spmi.2015.09.015

Cited by 6 publications

(4 citation statements)

References 27 publications

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“…The short channel effects (SCEs) which arise due to scaling of MOSFET is suppressed more in Dopingless AJ DG MOSFET, therefore improving the performance of the device. The I ON /I OFF ratio increases (~2.77x10 11 ), the ideal value of subthreshold slope (59.5 mV/V) and DIBL (10.5 mV/V) value is lowered. Analysis of Sensitivity between dopingless AJ DG MOSFET and AJ DG MOSFET with equal doping has been compared and observations are made.…”

Section: Read Operationmentioning

confidence: 99%

“…The various short channel effects arise due to parasitic capacitances, drain induced barrier lowering, mobility degradation, hot carrier effects etc. To overcome these effects the devices, need to be engineered using different techniques like gate engineering and channel engineering [2] [ [10][11][12][13][14]. Gate engineering includes changing the material of the gate with different work functions, designing double gate, triple gate and multi-gate structures.…”

Section: Introductionmentioning

confidence: 99%

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18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Mendiratta

Tripathi

2021

Silicon

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In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x 10 −6 A/μm with reduced OFF-state leakage current up to1.37 x 10 −17 A/μm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 K and 400 K shows a small variation in OFF-state current (<15%). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All the design and analysis has been done with a 2D/3D Visual TCAD device simulator.

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Section: Read Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Mendiratta

Tripathi

2021

Silicon

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“…Double trench MOSFETs (DT-MOSFET) are more favored because of their greater design flexibility and lack of process limitations for high-energy ion implantation [13][14][15][16]. Therefore, 4H-SiC DT-MOSFETs are one of the best power switching devices due to their extremely low on-resistance (Ron), high breakdown voltage (BV) and fast switching speed, etc [17,18].…”

Section: Introductionmentioning

confidence: 99%

A novel 4H-SiC multiple stepped SGT MOSFET with improved high frequency figure of merit

Zhang,

Luo,

et al. 2023

Phys. Scr.

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A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [Ron×Cgd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [Ron×Qgd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.

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“…It reduces the short channel effects, junction capacitance and provides dielectric isolation SOI (silicon on insulator) is also used in CMOS technology due to its high-speed performance and low power consumption [4] . Surround gates used in MOSFET allow more channel width which increases the drive current [5] . Capacitance model of material engineered CGT has also been proposed for improvement of short channel effects [6] .…”

Section: Introductionmentioning

confidence: 99%

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

Mendiratta¹,

Tripathi²

2020

J. Semicond.

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CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of I ON/I OFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of I OFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.

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Capacitance modeling of gate material engineered cylindrical/surrounded gate MOSFETs for sensor applications

Cited by 6 publications

References 27 publications

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

A novel 4H-SiC multiple stepped SGT MOSFET with improved high frequency figure of merit

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

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