18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Mendiratta, Namrata; Tripathi, Suman Lata

doi:10.1007/s12633-021-01417-5

Cited by 31 publications

(6 citation statements)

References 29 publications

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“…A comparison is made between the proposed GAA NC DL NW TFET and the literature as shown in table 4. We compare the proposed device with a set of normal (without NC application) devices, including a bulk planar conventional MOSFET [26], a dopingless asymmetrical junctionless double-gate MOSFET [27], an asymmetrical junctionless double-gate MOSFET [27], a double-gate MOSFET [28], a pocket (P+) double-gate MOSFET [28] and NC devices such as a negative capacitance charge plasma nanowire FET [17], a negative capacitance dopingless FET [20], a negative capacitance core-shell dopingless nanotube TFET [18], a negative capacitance charge plasma junctionless TFET [21], a PZTbased NC-TFET [29], and a Si:HfO2-based NC-TFET [29]. Ref.…”

Section: Resultsmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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In this paper, a novel low power consumption device based on dopingless gate all around nanowire tunnel field effect transistor with negative capacitance effect is proposed. Negative capacitance is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, VT and SS are dropped significantly to less than 60mV/decade. Negative capacitance makes significant contribution to the device performance by lowering operating voltage for low power applications. To calculate the optimum bias, Landau-Khalatnikov (L-K) equation has been used. To evaluate the influence of negative capacitance, ferroelectric (FE) material PZT (lead zirconate titanate) – ceramic material which has perovskite properties has been used as gate insulator. Thus, gate all around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA negative capacitance DL NW TFET (GAA NC DL NW TFET). PZT has an appropriate polarization rate, high dielectric capacitance and high degree of reliability. To achieve SS lower than 60mV/decade at lower VT, effective tuning of FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device structure. Aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of doping-less technique to the nanowire based TFET. The enhancement of the on-state current at reduced supply voltage of silicon based TFET devices with improved steep subthreshold swing which has been addressed with the help of NC technique. With the application of NC technique, the proposed device showcased an improved 4 (µA/µm) of ION, 1012 of current ratio. Additionally, influence of variation in FE thickness (tFE) on performance parameters are examined. The proposed device structure, GAA NC DL NW TFET operates at minimum operating voltage than GAA DL NW TFET making it as an ideal choice for low power voltage applications

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Section: Resultsmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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show abstract

“…The increase in leakage current is believed to be triggered by changes in process parameters. According to a previous study, the temperature can affect ionic current, causing an increase in off-state current and a decrease in the ION/IOFF current ratio, and it can also affect leakage current, causing an increase in leakage current due to the increase in heating current [15]. The process parameters employed in the design process, such as the VTH adjustment implantation, the threshold voltage (VTH) energy, the source/drain (S/D) implantation, and the S/D energy, must be optimized for a robust design.…”

Section: Introductionmentioning

confidence: 96%

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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In recent years, breakthroughs in electronics technology have upgraded the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy candidates due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene field effect transistor (FET) utilizing high-k and a metal gate, which are composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. Silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools are used to simulate the design and electrical properties, while Taguchi L9 orthogonal arrays (OA) are used to optimize the electrical properties. The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters, while the VTH adjustment tilt angle and the S/D implant tilt angle have been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap for semiconductors (ITRS) 2013 target.

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“…The fabrication of DG structure with perfectly aligned gate electrodes has been a critical issue in sub-100 nm regimes [18][19][20][21][22]. The effect of gate misalignment on the subthreshold characteristics and various analog/RF parameters of various junction-based and junctionless DG FETs has been presented in the literature [23][24][25][26][27][28][29][30][31][32]. It has been shown that misalignment primarily impacts the electrostatic strength of gate electrodes in the channel region which results in degraded subthreshold performance [23][24][25][26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

“…However, it has been noticed that most of these studies focusing on the effect of gate misalignment have been limited to investigating the subthreshold characteristics and/or analog/radio frequency (RF) performance parameters for different junctionless and junction-based FET structures [23][24][25][26][27][28][29][30][31][32]. To the best of our knowledge, the impact of gate misalignment in digital/analog circuits has yet not been studied extensively.…”

Section: Introductionmentioning

confidence: 99%

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

Kumar¹,

Chatterjee²,

Pandey³

2022

Semicond. Sci. Technol.

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In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2-D Silvaco ATLAS TCAD. With recessed silicon channel, the quantum confinement effects have been considered for channel thickness < 7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope, and lower drain-induced-barrier-lowering. Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of subthreshold slope and drain-induced-barrier-lowering with smaller variations of ~10.84% and ~61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different AC performance parameters namely, transconductance generation factor, unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ~9.67% and ~19.9%, respectively whereas the transconductance generation factor remains almost unaffected. Furthermore, to ensure the device capability in circuit application a CMOS inverter and common-source amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based common-source amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

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18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Cited by 31 publications

References 29 publications

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

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