Capacitive coupling and quantized feedback applied to conventional CMOS technology

Gabara, T.; Fischer, W.C.

doi:10.1109/cicc.1996.510559

Cited by 11 publications

(12 citation statements)

References 4 publications

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“…On the other hand, a high-density off chip I/O is a critical issue. The need for a 110µm pitch for costperformance area array flip-chip application is difficult to achieve with the available technology [4][5][6]. For the above reasons, this study needs to design a high-speed transceiver that consumes less power.…”

Section: Introductionmentioning

confidence: 98%

A 12 Gb/s chip-to-chip AC coupled transceiver

Wang

Hsieh

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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A differential AC coupled transceiver for high-speed and low-swing has been implemented in a 0.18µm CMOS process. The proposed architecture includes a pulse receiver and a broadband limiting amplifier to recover a NRZ signal from a 75fF capacitive coupled channel. The system works at 12Gb/s through 10cm FR4 printed circuit board interconnect, while dissipating only 13.5mW with a bit error rate less than 10 -12 .

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Section: Introductionmentioning

confidence: 98%

A 12 Gb/s chip-to-chip AC coupled transceiver

Wang

Hsieh

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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“…The use of capacitively coupled I/O and pulse signaling was proposed as one solution to this problem and has been investigated by numerous groups [1][2][3][4][5][6]. Capacitive coupling can be created by using on-chip metal-insulator-metal (MIM) capacitors, as reported in this paper, or by creating an inter-chip/package capacitor as reported in [7].…”

Section: Introductionmentioning

confidence: 98%

“…The work on board level capacitively coupled interconnect [1,5,6,8] and stacked ICs [2][3] have been reported as alternatives to physical pin/solder bumps for high density, low power chip-to-chip communications. Although transceiver design of capacitive coupling has been reported extensively, the data rate of capacitively coupled links is still lower than traditional high-speed serial links and the potential crosstalk associated with return-to-zero (RZ) pulse signaling has not been reported.…”

Section: Introductionmentioning

confidence: 99%

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

Luo

Wilson

Mick

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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A new differential pulse receiver is demonstrated for AC Coupled Interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter & 1.23pJ/bit for the receiver).

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“…In addition, unlike magnetically coupled schemes, the entire capacitively coupled circuit can be fabricated on a single integrated circuit to significantly reduce board space requirements. Capacitive coupling has been employed in bulk CMOS multi-chip modules to transfer data signals between multiple dies [7][8][9]. Capacitive coupling has also been used to pass data between isolated sections of a single die using a Silicon-on-Insulator (SOI) substrate [10].…”

Section: Introductionmentioning

confidence: 99%

A monolithic isolation amplifier in silicon-on-insulator CMOS: Testing and applications

Marcus

Strohben

Jaskulek

et al. 2006

Analog Integr Circ Sig Process

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In this paper, the design and test results of a 4-channel digital isolation amplifier are presented, along with results of a prototype power converter circuit using the amplifier for voltage feedback regulation. The amplifier uses a capacitive coupling technique to transfer digital signals from input to output while preserving galvanic isolation between the two. The isolation amplifier was fabricated in a 0.5 µm Silicon-on-Sapphire (SOS) technology and uses the isolation properties of the SOS substrate to achieve more than 800 V isolation between input and output grounds. Each of the four channels can operate in excess of 100 Mbps using a differential transmission scheme to reject ground bounce transients up to 1 V/µs. The input circuit can be powered from an on-chip charge-pump to permit single supply operation. The device can be used in a wide variety of applications that require passing signals across an isolation barrier: power supplies, remote sensing, and medical and industrial applications.

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Capacitive coupling and quantized feedback applied to conventional CMOS technology

Cited by 11 publications

References 4 publications

A 12 Gb/s chip-to-chip AC coupled transceiver

A 12 Gb/s chip-to-chip AC coupled transceiver

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

A monolithic isolation amplifier in silicon-on-insulator CMOS: Testing and applications

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