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Two 0.9pm CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (POI9 systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators (GVCOs), indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal, as shown in Figures 1 and 2 [1,21. Instantaneous phaselockingisguaranteedbyrestartingthegated oscillators every time input data transitions occur. As discussed in Reference [21, this method has been demonstrated to be precise

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