An analog 0.25 μm BiCMOS tailbiting MAP decoder

Moerz, M.; Gabara, T.; Yan, Ran; Hagenauer, J.

doi:10.1109/isscc.2000.839814

Cited by 63 publications

(46 citation statements)

References 1 publication

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“…A summary of this research was given in [27]. Recently, circuits similar to those of this paper were also proposed by Moerz et al [28], [29].…”

Section: Introductionmentioning

confidence: 59%

“…This decoder was actually implemented as an analog VLSI chip using the circuits of this correspondence [25], [26]. (A similar analog decoder for a two-state tail-biting code was implemented by Moerz et al [28].) The code is defined by the four-state tail-biting trellis consisting of nine identical trellis sections, each trellis section as shown in Fig.…”

Section: Sum-product Modulesmentioning

confidence: 99%

“…(The current mirrors can also be realized by standard quadratic-law CMOS transistors, in which case they may be viewed as square-root current-to-voltage converters followed by quadratic voltage-to-current converters.) Indeed, Moerz et al [28] prefer to describe their circuit modules-which use the circuit of Fig. 8 without the dashed box-in terms of voltages.…”

Section: Example 2 (Continued)mentioning

confidence: 99%

See 2 more Smart Citations

Probability propagation and decoding in analog VLSI

Loeliger

Lustenberger

Helfenstein³

et al. 2001

IEEE Trans. Inform. Theory

129

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“…A summary of this research was given in [27]. Recently, circuits similar to those of this paper were also proposed by Moerz et al [28], [29].…”

Section: Introductionmentioning

confidence: 59%

Section: Sum-product Modulesmentioning

confidence: 99%

Section: Example 2 (Continued)mentioning

confidence: 99%

See 1 more Smart Citation

Probability propagation and decoding in analog VLSI

Loeliger

Lustenberger

Helfenstein³

et al. 2001

IEEE Trans. Inform. Theory

129

View full text Add to dashboard Cite

show abstract

“…A good example of this is the application of analog computing to decoders. It has been demonstrated that continuous-time, continuous-valued analog signal processing is well suited to developing high-speed, low-power, and areaefficient decoders [2][3][4][5][6][7][8]. In this paper we describe and present new results for a new decoding method, inspired by analog decoding, called stochastic decoding [9].…”

Section: Introductionmentioning

confidence: 99%

Stochastic Implementation of LDPC Decoders

Gross

Gaudet²,

Milner³

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

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Abstract-LDPC codes are found in many recent communications standards such as 10GBASE-T, We present a review of a new class of "stochastic" iterative decoding architectures. Stochastic decoders represent probabilistic messages by the frequency of ones in a binary stream. This results in a simple mapping of the factor graph of the code into silicon. An FPGA implementation of a LDPC decoder with 8 information bits and 8 coded bits is described. On an Altera Cyclone FPGA, the throughput is 5 Mbps when clocked at 100 MHz and is expected to increase nearly linearly with the code length. Simulations of the decoder on an Altera Stratix FPGA indicate a potential throughput of 8 Mbps.

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“…These values iterate throughout the network to some final steady state to yield the decision. Decoders that use subthreshold mode networks and its variants were first realized by [4] and subsequently by [5,6,7,8] as an alternative to increasingly complex digital implementations.…”

Section: Introductionmentioning

confidence: 99%

A 0.8V CMOS analog decoder for an (8,4,4) extended Hamming code

Nguyen

Winstead

Gaudet

et al.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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A novel way to decode error control codes is through the use of analog circuits. Decoders exploit the non ideal behaviour of transistors operating in the subtheshold mode to process probability information. This paper describes the design of an (8,4,4) extended Hamming decoder operating at supply voltage 0.8V using 0.18µm CMOS technology. When biased at 1 µA, a decoding rate of 444 kbps and energy per decoded bit of 0.64 nJ/b is achieved.

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An analog 0.25 μm BiCMOS tailbiting MAP decoder

Cited by 63 publications

References 1 publication

Probability propagation and decoding in analog VLSI

Probability propagation and decoding in analog VLSI

Stochastic Implementation of LDPC Decoders

A 0.8V CMOS analog decoder for an (8,4,4) extended Hamming code

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