Abstract-The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

Abstract-The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

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A new clock-feedthrough compensation scheme for switchedcurrent circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S S S 2 I I I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

In this work, a frequency-based model is presented to examine limit cycle and spurious behavior in a bang-bang all-digital phase locked loop (BB-ADPLL). The proposed model considers different type of nonlinearities such as quantization effects of the digital controlled oscillator (DCO), quantization effects of the bang-bang phase detector (BB-PD) in noiseless BB-ADPLLs by a proposed novel discrete-time model. In essence, the traditional phase-locked model is transformed into a frequency-locked topology equivalent to a sigma delta modulator (SDM) with a dc-input which represents frequency deviation in phase locked state. The frequency deviation must be introduced and placed correctly within the proposed model to enable the accurate prediction of limit cycles. Thanks to the SDM-like topology, traditional techniques used in the SDM nonlinear analysis such as the discrete describing function (DDF) and number theory can be applied to predict limit cycles in first and second-order BB-ADPLLs. The inherent DCO and reference phase noise can also be easily integrated into the proposed model to accurately predict their effect on the stability of the limit cycle. The results obtained from the proposed model show good agreement with time-domain simulations.