Improved two-step clock-feedthrough compensation technique for switched-current circuits

Abstract

A new clock-feedthrough compensation scheme for switchedcurrent circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S S S 2 I I I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

High speed switched-current memory cell with very low offset and charge injection errors

“…Most of them generate an extra current error at output node which contains signal dependent part, offset or both of them. These techniques are mostly complicated due to containing complex structure and clock circuit [8][9][10][11].…”

“…To minimize the error, several techniques have been proposed. Some of them are based on generating additional error currents to cancel the original one at the output [8][9][10][11]. Attenuation, algorithmic, adaptive and zero-voltage switching are the other presented techniques but for achieving a complete cancelation (only in theory), complicated circuit and/or clock scheme techniques are unavoidable.…”

Optimizing performances of switched current memory cells through a heuristic

“…During the restitution phase, this switch is opened and ideally, the gate potential is hold equal to the value reached at the end of the acquisition time. Switching of the transistor voltage switch causes a transfer of the charges to the gate of the memory transistor [9,10]. These charges were previously present in the channel of this transistor when it was at the conduction state.…”

Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink

“…The thermal noise is present in all circuit elements containing resistor [16], a MOS transistor operating in the saturation region identical to a passive resistor between its drain and source terminals (the inversed channel), Thermal noise is caused by the random thermal motion of carriers in the channel [18], the short circuit thermal noise current spectral density Id is then given by (08) Where k is the Boltzman constant, T represents the absolute temperature, and gm is the transconductance of the MOS transistor, this noise model is valid only for long channel devices, the new thermal noise in MOS transistors models have been described in the literature [19][20] In small geometry devices the thermal noise was modeled as…”