Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator

Abstract

We investigated the effect of the presence of strained SiGe layer inserted between unstrained Si and buried oxide layer and the Ge concentration in strained SiGe layer on the memory margin of capacitor-less memory-cell. We observed that memory margin of unstrained Si on strained SiGe-on-insulator capacitor-less memory-cells increases with the Ge concentration of the strained SiGe layer and obtained memory margin at the Ge concentration of 19 at% that was 3.2 times larger than that at the silicon-on-insulator capacitor-less memory-cell. This enhancement was due to the potential-barrier lowering increasing exponentially with the Ge concentration resulting from higher hole confinement in spite of the reduction in the saturated drain current.

Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

“…Ge concentration, as shown in figure 3(a). In addition, the potential barrier lowering at the source edge of the capacitorless memory cell, measured by the difference in V T between 0.05 and 1 V drain voltages, increased exponentially with increasing Ge concentration of the relaxed SiGe layer, which is of the same trend as for the unstrained Si ε-SGOI capacitorless memory cell [15]. In general, the memory margin of the capacitor-less memory cell is determined by the amount accumulated holes below the source of the capacitor-less memory cell resulting in the potential barrier lowering at the source edge of the capacitor-less memory cell and then the kink effect occurs; thus, a bigger amount of potential barrier lowering produces a higher drain current after the kink effect occurs, leading to a higher margin of the capacitor-less memory cell.…”

“…In particular, it was reported that the insertion of a strained SiGe layer between the Si channel and the buried oxide layer for a capacitor-less memory cell fabricated on the unstrained Si channel on the strained SiGe layer-on-insulator (unstrained Si ε-SGOI capacitor-less memory cell) resulted in confining more holes at the source edge and enhancing the memory margin of the capacitor-less memory cell, although the electron mobility of the unstrained Si ε-SGOI capacitor-less memory cell was degraded by inserting a strained SiGe layer. This is called the hole confinement effect [15,16]. In addition, it was reported that the introduction of a tensile strain Si channel for a capacitor-less memory cell fabricated on the strained Si channel-on-insulator (strained Si ε-SOI capacitor-less memory cell) resulted in increasing the electron mobility of the Si channel and enhancing the memory margin of the capacitorless memory cell.…”

Two-terminal vertical thyristor using Schottky contact emitter to improve thermal instability

“…Alternatively, the one transistor (T)-DRAM, fabricated with a fully depleted silicon-on-insulator (FDSOI) n-MOSFET and three electrodes (i.e. gate, source, and drain), has been proposed [8][9][10][11]. However, it also faces the scaling-down issue of an FDSOI n-MOSFET similar to an n-MOSFET of the DRAM cells because it has a fundamental memory cell size of 6F 2 , which cannot be reduced to 4F 2 (F represents the minimum feature size).…”

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

“…Note that the Si channel thickness in FD SOI n-MOSFETs is several tens of nanometers, and a specific thickness and doping concentration in the silicon channel exhibits the maximum memory margin. To enhance the memory margin of capacitor-less memory cells further, a capacitor-less memory cell fabricated with a FD n-MOSFET on an unstrained Si channel on a nano-scale strained SiGe-oninsulator (called a FD unstrained silicon ε-SGOI n-MOSFET) has been proposed [12]. The inserted strained SiGe layer introduced more hole confinement by lowering the potential barrier at the interface between the strained SiGe layer and buried oxide.…”