A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

Abstract

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.

Design of n+-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector

“…To overcome the scaling-down limit beyond the DRAM cell design rule of less than 10 nm, a capacitor-less memory cell, called a 1-transistor (1T)-DRAM, has been proposed. Note that a 1T-DRAM can perform DRAM cell operations by utilizing the kink effect for a fully depleted silicon-on-insulator (FD SOI) n-MOSFET [14]. The feasibility of a 1T-DRAM satisfying the memory cell design rule of less than 10 nm has been demonstrated by the nonnecessity of a selector and a simple capacitor structure and suggests the possibility of multi-level cell operation.…”

Two-terminal vertical thyristor using Schottky contact emitter to improve thermal instability

“…Alternatively, the one transistor (T)-DRAM, fabricated with a fully depleted silicon-on-insulator (FDSOI) n-MOSFET and three electrodes (i.e. gate, source, and drain), has been proposed [8][9][10][11]. However, it also faces the scaling-down issue of an FDSOI n-MOSFET similar to an n-MOSFET of the DRAM cells because it has a fundamental memory cell size of 6F 2 , which cannot be reduced to 4F 2 (F represents the minimum feature size).…”

Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

“…It has been reported that scaling-down below the half-pitch size of 20 nm would be the physical limit of the conventional memory cell structure, consisting of one n-metal-oxide-semiconductor field-effect transistor (n-MOSFET) and one cylindrical capacitor, because the capacitors of the DRAM cells would collapse on one another [4][5][6][7][8]. The capacitor-less memory cell is a promising candidate to overcome the limitation of the conventional DRAM cell structure, being produced by just one n-MOSFET fabricated on a silicon-on-insulator (SOI) substrate and performing volatile memory cell operation [9][10][11]17]. Many research works improving the retention time (or memory margin) of capacitor-less memory cells have been reported [12][13][14]17].…”

“…The capacitor-less memory cell is a promising candidate to overcome the limitation of the conventional DRAM cell structure, being produced by just one n-MOSFET fabricated on a silicon-on-insulator (SOI) substrate and performing volatile memory cell operation [9][10][11]17]. Many research works improving the retention time (or memory margin) of capacitor-less memory cells have been reported [12][13][14]17]. In particular, it was reported that the insertion of a strained SiGe layer between the Si channel and the buried oxide layer for a capacitor-less memory cell fabricated on the unstrained Si channel on the strained SiGe layer-on-insulator (unstrained Si ε-SGOI capacitor-less memory cell) resulted in confining more holes at the source edge and enhancing the memory margin of the capacitor-less memory cell, although the electron mobility of the unstrained Si ε-SGOI capacitor-less memory cell was degraded by inserting a strained SiGe layer.…”

“…In addition, it was reported that the introduction of a tensile strain Si channel for a capacitor-less memory cell fabricated on the strained Si channel-on-insulator (strained Si ε-SOI capacitor-less memory cell) resulted in increasing the electron mobility of the Si channel and enhancing the memory margin of the capacitorless memory cell. This is called the strained Si channel effect [17].…”