Design of n⁺-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector

Abstract

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (I on /I off ) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a 1 / 3 bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Two-terminal vertical thyristor using Schottky contact emitter to improve thermal instability

“…the sequence of a shorter depletion width is followed by W (30.2 nm), Ti (33.6 nm), Ta (35.2 nm), and Al (37.5 nm). Consequently, a higher metal work function results in a higher V LU because it produces a longer neutral p + -base-Si width [22]. Thus, the sequence of a higher V LU is followed by W (3.26 V), Ti (3.10 V), Ta (3.08 V), and Al (3.04 V).…”

“…A two-terminal-electrode vertical thyristor used as a 3D cross-point memory-cell without a selector was demonstrated [21][22][23][24][25] to meet the requirement for a high switching speed (i.e. several tens of ns [26]) without the use of a selector.…”

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

“…In a lateral gate-all-around (GAA) silicon nanowire design, the expected cell size is comparable to the traditional DRAM cell (8 F 2 ), where F is the minimum feature size [ 5 ]. Moreover, the 1T DRAM cell has the potential to be fabricated in a vertical channel [ 28 ], and the expected cell size is 4 F 2 .…”

“…feature size [5]. Moreover, the 1T DRAM cell has the potential to be fabricated in a vertical channel [28], and the expected cell size is 4 F 2 .…”