We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross-point memory cell without a selector from the viewpoints of p+- and n+-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p++-emitter/n+-base/p+-base/n++-emitter or n++-emitter/p+-base/n+-base/p++-emitter. The proper p+- and n+-base-region width (i.e., 160 nm) and p++-emitter/n+-base/p+-base/n++-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n++-emitter and p+-base or n+-base and p++-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than ∼4 × 10−4.

Tunnel field-effect transistors (TFETs) have attracted immense interest as a promising alternative to complementary metal–oxide semiconductors for low-power-consumption applications. However, conventional TFETs introduce both random dopant fluctuations and ambipolar current issues at negative gate voltages for sub-6-nm technology nodes. In this study, we address the performance of charge plasma-driven doping-less TFETs, including sub-3-nm thick compact drain (CD) geometry/SiGe-channel/Ge source layers for suitable bandgap engineering. An ultrathin CD frame and heteromaterials are adopted for use as channels/sources to improve the ambipolarity and ON-state features, respectively. Simulation demonstrates a clear reduction in the ambipolar current from 3.3 × 10−14 to 3.0 × 10−17 A at gate (VG)/drain (VD) voltages of −1.5/1.0 V and an enhancement in the ON-current from 2.0 × 10−5 to 8.6 × 10−5 A at VG = 1.5 and VD = 1.0 V, compared with conventional TFETs. In addition, diverse fabrication-friendly metals applicable to industry fieldwork sites are tested to determine how the metal work functions influence the outputs. The use of Ti/W/Ni as the drain/channel/source materials, respectively, yields an enhanced ambipolar current of 1.2 × 10−20 A and an ON-current of 3.9 × 10−5 A.

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (I on /I off ) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a 1 / 3 bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Thyristor random access memory without a capacitor has been highlighted for its significant potential to replace current dynamic random access memory. We fabricated a two-terminal (2-T) thyristor by wet chemical etching techniques on n+–p–n–p+ silicon epitaxial layers, which have the proper thicknesses and carrier concentrations, as provided by technology computer-aided design simulation. The etched features such as etch rate, surface roughness, and morphologies, in a potassium hydroxide (KOH) and an isotropic etchant, were compared. The type of silicon etchant strongly affected the etched shapes of the side wall and therefore critically influenced the device performance with varying turn-on voltages. The turn-on voltage of thyristor fabricated with a KOH solution showed a consistent tendency of operation voltage in the range of 2.2–2.5 V regardless of the cell size, while the thyristor formulated with isotropic etchant had an operation voltage which increased from about 2.3–4.4 V as the device dimension decreased from 200 μm to 10 μm. The optimized 2-T thyristor showed a memory window of about 2 V, a nearly zero-subthreshold swing, and a current on-off ratio of about 104–105.