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We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross-point memory cell without a selector from the viewpoints of p+- and n+-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p++-emitter/n+-base/p+-base/n++-emitter or n++-emitter/p+-base/n+-base/p++-emitter. The proper p+- and n+-base-region width (i.e., 160 nm) and p++-emitter/n+-base/p+-base/n++-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n++-emitter and p+-base or n+-base and p++-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than ∼4 × 10−4.

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The low field electron mobility in n-type HgCdTe is calculated by using the relaxation time approximation method. Scattering mechanisms considered in the analysis are ionized impurity, electron–hole, alloy, and polar optical-phonon (two types) scatterings. The calculation also retains band-structure effects such as nonparabolic conduction band, electron wave function admixture, and velocity degradation as the electron energy increases. Furthermore, degeneracy is incorporated without approximation. For polar optical-phonon momentum relaxation time, we employ a model that can be applicable at low temperature, when the thermal energy is lower than the optical-phonon energy. The calculation results for drift mobility are in good agreement with the Monte Carlo results. The effects of donor level, compensation, and ionicity of impurity on Hall mobility are also presented.

Tunnel field-effect transistors (TFETs) have attracted immense interest as a promising alternative to complementary metal–oxide semiconductors for low-power-consumption applications. However, conventional TFETs introduce both random dopant fluctuations and ambipolar current issues at negative gate voltages for sub-6-nm technology nodes. In this study, we address the performance of charge plasma-driven doping-less TFETs, including sub-3-nm thick compact drain (CD) geometry/SiGe-channel/Ge source layers for suitable bandgap engineering. An ultrathin CD frame and heteromaterials are adopted for use as channels/sources to improve the ambipolarity and ON-state features, respectively. Simulation demonstrates a clear reduction in the ambipolar current from 3.3 × 10−14 to 3.0 × 10−17 A at gate (VG)/drain (VD) voltages of −1.5/1.0 V and an enhancement in the ON-current from 2.0 × 10−5 to 8.6 × 10−5 A at VG = 1.5 and VD = 1.0 V, compared with conventional TFETs. In addition, diverse fabrication-friendly metals applicable to industry fieldwork sites are tested to determine how the metal work functions influence the outputs. The use of Ti/W/Ni as the drain/channel/source materials, respectively, yields an enhanced ambipolar current of 1.2 × 10−20 A and an ON-current of 3.9 × 10−5 A.