Cardiac arrhythmia refers to irregular heartbeats caused by anomalies in electrical transmission in the heart muscle, and it is an important threat to cardiovascular health. Conventional monitoring and diagnosis still depend on the laborious visual examination of electrocardiogram (ECG) devices, even though ECG signals are dynamic and complex. This paper discusses the need for an automated system to assist clinicians in efficiently recognizing arrhythmias. The existing machine‐learning (ML) algorithms have extensive training cycles and require manual feature selection; to eliminate this, we present a novel deep learning (DL) architecture. Our research introduces a novel approach to ECG classification by combining the vision transformer (ViT) and the capsule network (CapsNet) into a hybrid model named ViT‐Cap. We conduct necessary preprocessing operations, including noise removal and signal‐to‐image conversion using short‐time Fourier transform (SIFT) and continuous wavelet transform (CWT) algorithms, on both normal and abnormal ECG data obtained from the MIT‐BIH database. The proposed model intelligently focuses on crucial features by leveraging global and local attention to explore spectrogram and scalogram image data. Initially, the model divides the images into smaller patches and linearly embeds each patch. Features are then extracted using a transformer encoder, followed by classification using the capsule module with feature vectors from the ViT module. Comparisons with existing conventional models show that our proposed model outperforms the original ViT and CapsNet in terms of classification accuracy for both binary and multi‐class ECG classification. The experimental findings demonstrate an accuracy of 99% on both scalogram and spectrogram images. Comparative analysis with state‐of‐the‐art methodologies confirms the superiority of our framework. Additionally, we configure a field‐programmable gate array (FPGA) to implement the proposed model for real‐time arrhythmia classification, aiming to enhance user‐friendliness and speed. Despite numerous suggestions for high‐performance FPGA accelerators in the literature, our FPGA‐based accelerator utilizes optimization of loop parallelization, FP data, and multiply accumulation (MAC) unit. Our accelerator architecture achieves a 57% reduction in processing time and utilizes fewer resources compared to a floating‐point (FlP) design.
