Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization

Abstract

In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization.

Graphene nanoribbon FETs: Technology exploration and CAD

“…One of the main candidate approaches is the physics-based, semianalytical nanotransistor model based on the Landauer approach that has previously been applied to model silicon nanoscale MOSFETs, nanowire FETs, and CNTFETs [26,[30][31][32][33][34][35][36][37]. Circuit models based on the Landauer approach provide a compact physical description of transistor physics at the mesoscopic and molecular scale.…”

Compact Modeling of Carbon Nanotube Transistor and Interconnects

“…All existing models (Castro et al, 2002;Deng & Wong, 2007a;Guo et al, 2004;Raychowdhury et al, 2004;Wong et al, Nov. www.intechopen.com …”

“…However, it requires self-consistent numerical iterations to calculate the final current and tunneling probability. Currently most of the models developed for carbon nanotube transistors and interconnects employ some kind of numerical approach (Guo et al, 2004;Wong et al, Nov. 2006) to obtain the I-V and C-V characteristics. Though highly physical and accurate, such numerical approaches reduce the computation efficiency and are not suitable for large-scale circuit simulations.…”

Design and modeling of nonvolatile memories by resistive switching elements

“…However, if accomplished by utilizing a SB-CNTFET [101] (as equivalent to the macromodel of the ambipolar transistor of Figure 124), the delay of the comparison circuit can be significantly reduced because [101] has shown that the inverter delay of a SB-CNTFET at a diameter of 1nm, is nearly 1ps.…”

“…For the average power dissipation of the comparison circuit (CAM and TCAM cells), the macromodel of the ambipolar transistor ( Figure 124) is used; this is a very pessimistic value, because the power dissipation in Table 70 accounts for the 10 transistors used in this macromodel ( Figure 124) rather than the power dissipation of a fabricated device (using for example a single CNTFET [101]). The average power dissipation and the PDP of both comparator circuits made of a single CNTFET should be even lower than the values obtained for the macromodel of the ambipolar transistor ( Figure 124).…”