Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation

Erniyazov, Sarvarbek; Jeon, Jun-Cheol

doi:10.1016/j.mee.2019.03.015

Cited by 57 publications

(19 citation statements)

References 16 publications

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“…33 % area reduction and 23 % cell-complexity reduction than a 2019's published similar component [15] is possible in this proposed one bit "Full-Adder-Subtractor" design. Multilayer multi-bit (up to 4-bit) design formation using the proposed reversible multilayer single-bit structure is also shown in this paper, where a RCA is presented with ripple-borrow-output and this feature is more advance to reduce the area, delay, design-cost and cell-complexity with less power-dissipation compare to previously published 4-bit CLA and CSA design [6]. This design can reduce 81 % of area-occupation, 77 % AUF, 74 % cell-complexity, 33 % delay and 91 % design-cost compare to the given advanced 4-bit adder design (CSA) in a previous work.…”

Section: Discussionmentioning

confidence: 90%

“…The transmission line between them is placed in 2 nd layer. The parametric investigation of this 4-bit proposed design is presented in the next portion of this paper with a simulated outcome and a clear parametric-comparison among the presented design (RCA with RBS) and previously published CLA and CSA [6].…”

Section: Design Of Proposed "Full-adder-subtractor" Structure After Single-bit To Multi-bit Conversionmentioning

confidence: 99%

“…But presently, the improvement of "QCA" based logical structures becomes a big challenge. Thus, in this paper, reversible gate is chosen in multilayer platform to bring more advancement of our proposed "Adder-Subtractor" physicalformation and this multibit design of proposed advanced adder with subtraction operation is more acceptable than other advanced adder circuits, such as "Carry Look Ahead Adder" or CLA and "Carry Save Adder" or CSA [6] due to the better occupied-area, delay and energy-dissipation reduction capability of our proposed design compare to other discussed designs. This design also maintains the outputstrength effectively at high-temperature with high faulttolerance and low quantum-cost in multilayer 3D platform due to the presence of reversible gates, which follow the adiabatic logic [7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Sarkar¹

2021

pae

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.

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Section: Discussionmentioning

confidence: 90%

Section: Design Of Proposed "Full-adder-subtractor" Structure After Single-bit To Multi-bit Conversionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Sarkar¹

2021

pae

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“…A coplanar QCA full adder is studied and implemented in [18] for low energy dissipation. The efficient 3 input XOR gate are implemented as a coplanar QCA technique in [19].…”

Section: Related Workmentioning

confidence: 99%

Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

Pathak*,

Singh

2020

IJRTE

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Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 µm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved

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“…Combination circuits such as multiplexers and full adders and sequential circuits such as flip-flops, counters, and memories can all be easily implemented visually in accordance with quantum logic [ 6 , 7 , 8 , 9 , 10 ]. Above all, if the structure of an operator such as adder, subtractor, multiplier, divider, and inverter increases, delay time, space complexity, and energy dissipation must be seriously considered in circuit configuration [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ].…”

Section: Introductionmentioning

confidence: 99%

Non-Restoring Array Divider Using Optimized CAS Cells Based on Quantum-Dot Cellular Automata with Minimized Latency and Power Dissipation for Quantum Computing

Kim

Jeon

2022

Nanomaterials

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Many studies have addressed the physical limitations of complementary metal-oxide semi-conductor (CMOS) technology and the need for next-generation technologies, and quantum-dot cellular automata (QCA) are emerging as a replacement for nanotechnology. Meanwhile, the divider is the most-used circuit in arithmetic operations with squares and multipliers, and the development of effective dividers is crucial for improving the efficiency of inversion and exponentiation, which is known as the most complex operation. In most public-key cryptography systems, the corresponding operations are used by applying algebraic structures such as fields or groups. In this paper, an improved design of a non-restoring array divider (N-RAD) is proposed based on the promising technology of QCA. Our QCA design is focused on the optimization of dividers using controlled add/subtract (CAS) cells composed of an XOR and full adder. We propose a new CAS cell using a full adder that is designed to be very stable and compact so that power dissipation is minimized. The proposed design is considerably improved in many ways compared with the best existing N-RADs and is verified through simulations using QCADesigner and QCAPro. The proposed full adder reduces the energy loss rate by at least 25% compared to the existing structures, and the divider has about 23%~4.5% lower latency compared to the latest coplanar and multilayer structures.

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Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation

Cited by 57 publications

References 16 publications

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

Non-Restoring Array Divider Using Optimized CAS Cells Based on Quantum-Dot Cellular Automata with Minimized Latency and Power Dissipation for Quantum Computing

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