CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays

Agrawal, Amogh; Kosta, Adarsh Kumar; Kodge, Sangamesh; Kim, Dong Eun; Roy, Kaushik

doi:10.1109/jetcas.2020.3014250

Cited by 18 publications

(9 citation statements)

References 33 publications

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“…Agrawal et al [54] designed an 8 TB SRAM Chiplet, which uses parasitic capacitance for accumulating voltages and dot product calculation. The energy-delay product (EDP) is 38% lower than that of Von Neumann computing systems within the acceptable accuracy degradation range (1-5%), as shown in Figure 7a.…”

Section: Pim Architectures Based On Mainstream Memorymentioning

confidence: 99%

“…Processing-in-memory (PIM) can complete the data computing and storage in memory with high power efficiency in computation-intensive applications [51][52][53]. In addition, 3D memory architecture shortens the data transmission path by vertically stacking multiple Chiplets compared with 2D storage architecture and effectively reduces the energy consumption and improves the thermal reliability [54].…”

Section: Memory Architecture For Processing Datamentioning

confidence: 99%

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Architecture of Computing System based on Chiplet

et al. 2022

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Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

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Section: Pim Architectures Based On Mainstream Memorymentioning

confidence: 99%

Section: Memory Architecture For Processing Datamentioning

confidence: 99%

Architecture of Computing System based on Chiplet

et al. 2022

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“…Many approaches to Logic-In-Memory can be found in literature; however, two main approaches can be distinguished. The first one can be classified as Near-Memory Computing (NMC) [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], since the memory inner array is not modified and logic circuits are added at the periphery of this; the second one can be denoted as Logic-in-Memory (LiM) [19][20][21][22][23][24][25][26][27][28], since the memory cell is directly modified by adding logic circuits to it.…”

Section: Introductionmentioning

confidence: 99%

“…Many applications can benefit from the IMC approach, such as machine learning and deep learning algorithms [4,6,[8][9][10][11][12]14,15,19,[21][22][23][24], but also general purpose algorithms [2,5,7,13,[16][17][18]20,25,26]. For instance: in [19], a 6T SRAM cell is modified by adding two transistors and a capacitor to it, in order to perform analog computing on the whole memory, which allows to implement approximated arithmetic operations for machine learning algorithms; in [18], logic layers consisting of latches and LUTs are interleaved with memory ones in an SRAM array, in order to perform different kinds of logic operations directly inside the array; in [26], the pass transistors of the 6T SRAM cell are modified to perform logic operations directly in the cell, which allows the memory to function as an SRAM, a CAM (Content Addressable Memory) or a LiM architecture.…”

Section: Introductionmentioning

confidence: 99%

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

et al. 2021

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The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories.

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“…IMC sees data and compute as codependent entities, thereby allowing the possibility of computation in situ in the memory array. Implementing the Multiply and Accumulate (MAC) computation in memory has been the key focus of several IMC approaches in the recent past [7][8][9][10][11]. Techniques to compute the MAC in current domain [8], charge domain [9] and time-domain [11] were analyzed in these IMC approaches.…”

Section: Introductionmentioning

confidence: 99%

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter

Vijayakumar

Viraraghavan

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Area and energy-efficient data converters are an integral part of In-Memory Compute (IMC) engines. The conventional Digital to Analog Converters (DACs) uses binary-weighted pull-up current sources with scan-flops feeding in the digital input. These bulky pull-up devices and scan-flops make it hard to integrate along-side a memory array in an area-efficient manner. Further, it is prone to error due to local variations owing to limited digital control. In this paper, we propose an area-efficient, Word-Line (WL) pitch-aligned, layout friendly In-Memory compatible DAC (IM-DAC), whose layout resembles the 8T SRAM array very closely, thus achieving memory array-like density. Simulation results show that the worst-case INL and DNL is 2.42 LSB and -0.32 LSB, respectively. We obtained a 3.4X area advantage in comparison with the conventional DAC. The highdensity layout allows for additional calibration pull-up stacks, with minimal area penalty, that reduces the standard deviation of the linearized-current to 48.76% of the corresponding value before calibration.

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CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays

Cited by 18 publications

References 33 publications

Architecture of Computing System based on Chiplet

Architecture of Computing System based on Chiplet

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter

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